Page history
9 June 2024
10 July 2023
9 July 2023
5 May 2023
7 March 2022
25 December 2020
2 August 2018
osdev>Nullplan
→Protected Mode Registers: Added stub chapter about the TR, since we have one about the LDTR.
+57
osdev>Nullplan
→MSRs: Added FS and GS segment base registers
+663
11 March 2018
27 December 2017
7 June 2017
osdev>Eladashkcenazi335
→CR4
+1
osdev>Eladashkcenazi335
→CR4
+1
osdev>Eladashkcenazi335
→CR4
+14
osdev>Eladashkcenazi335
→Control Registers
+78
osdev>Eladashkcenazi335
→CR0
+3
osdev>Eladashkcenazi335
→CR0
+12
osdev>Eladashkcenazi335
→CR0
+476
3 September 2016
12 August 2016
25 July 2016
5 July 2016
osdev>Halofreak1990
→Updated CR3 description for 64-bit
−81
osdev>Halofreak1990
→Added CR8 register description
+1,218
9 March 2016
3 February 2016
osdev>Halofreak1990
→Pointer Registers: Updated registers with 8-bit addressing
+23
osdev>Halofreak1990
→Index Registers: Updated registers with 8-bit addressing
+21
osdev>Halofreak1990
→General Purpose Registers: Updated list with r8 - r15
+261
10 January 2016
15 December 2015
2 May 2015
1 May 2015
30 April 2015
osdev>Glauxosdev
→EFER
+2
osdev>Glauxosdev
→EFER
m−14
osdev>Glauxosdev
No need to show assembly instruction.
m−21
osdev>Glauxosdev
Tablify DR7
m+181
osdev>Glauxosdev
Consistent EFER, someday I may capitalize every label.
m−45
osdev>Glauxosdev
moved CPU Registers (x86-64) to CPU Registers x86-64: No parenthesis needed
mRoman
Created page with "CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data. ==General purpose registers== {| {{wikitable}} |- ! 64 bit ! 32 ..."
+5,515