CPU Registers x86-64

CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.

General purpose registers

64 bit	32 bit	16 bit	8 high bit	8 low bit	description
rax	eax	ax	ah	al	accumulator
rbx	ebx	bx	bh	bl	base
rcx	ecx	cx	ch	cl	counter
rdx	edx	dx	dh	dl	data

Segment registers

16 bit	description
cs	code segment
ds	data segment
es, fs, gs	extra segment
ss	stack segment

Index registers

64 bit	32 bit	16 bit	description
rsi	esi	si	source index
rdi	edi	di	destination index

Pointer registers

64 bit	32 bit	16 bit	description
rbp	ebp	bp	base pointer
rsp	esp	sp	stack pointer
rip			instruction pointer

RFLAGS register

bit	label	description
0	cf	carry flag
2	pf	parity flag
4	af	auxiliary flag
6	zf	zero flag
7	sf	sign flag
8	tf	trap flag
9	if	interrupt flag
10	df	direction flag
11	of	overflow flag
12-13	iopl	i/o priviledge level
14	nt	nested task flag
16	rf	resume flag
17	vm	virtual 8086 mode flag
18	ac	alignment check flag
19	vif	virtual interrupt flag
20	vip	virtual interrupt pending
21	id	id flag

Control registers

CR0

bit	label	description
0	pe	protected mode enable
1	mp	monitor co-processor
2	em	emulation
3	ts	task switched
4	et	extension type
5	ne	numeric error
16	wp	write protect
18	am	alignment mask
29	nw	not-write through
30	cd	cache disable
31	pg	paging

CR1

Reserved

CR2

bit	label	description
0-31	pfla	page fault linear address

CR3

bit	description	PAE mode	long mode
0-31	physical base address of page directory	base of PDPT	base of PML4T

Note that this must be page aligned

CR4

bit	label	description
0	vme	virtual 8086 mode extensions
1	pvi	protected mode virtual interrupts
2	tsd	time stamp disable
3	de	debugging extensions
4	pse	page size extension
5	pae	physical address extension
6	mce	machine check exception
7	pge	page global enable
8	pce	performance monitoring counter enable
9	osfxsr	os support for fxsave and fxrstor instructions
10	osxmmexcpt	os support for unmasked simd floating point exceptions
13	vmxe	virtual machine extensions enable
14	smxe	safer mode extensions enable
17	pcide	pcid enable
18	osxsave	xsave and processor extended states enable
20	smep	supervisor mode executions protection enable
21	smap	supervisor mode access protection enable

EFER

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel. Its MSR number is 0xC0000080.

Bit	Purpose
63:16	Reserved
15	TCE (Translation Cache Extension)
14	FFXSR (Fast FXSAVE/FXRSTOR)
13	LMSLE (Long Mode Segment Limit Enable)
12	SVME (Secure Virtual Machine Enable)
11	NXE (No-Execute Enable)
10	LMA (Long Mode Active)
9	Reserved
8	LME (Long Mode Enable)
7:1	Reserved
0	SCE (System Call Extensions)

Debug registers

DR0 - DR3

Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.

DR6

It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.

DR7

DR7 controls breakpoint conditions. The low order 8 bits enable the four breakpoints. Bit 0 enables breaking at DR0 locally, Bit 1 enables a global breakpoint on DR0, Bit 2,3 for DR1 and so on. A local breakpoint bit deactivates on hardware task switches, globals do not. Bits 16-17 determine conditions for DR0, 20-21 for DR1, 24-25 for DR2 and 28-29 for DR3. In these bits, 00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported). Bits 18-19 determine the size of the DR0 breakpoint, 22-23 for DR1, 26-27 for DR2 and 30-31 for DR3. TODO

Test registers

name	description
TR3 - TR5	undocumented
TR6	test command register
TR7	test data register

Pmode segmentation registers

GDTR

bits	label	description
0-15	limit	size of GDT
16-47	base	starting address of GDT

LDTR

Stores the segment selector of the LDT. It is set with LLDT.

IDTR

bits	label	description
0-15	limit	size of IDT
16-47	base	starting address of IDT