CPU Registers x86-64

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General Purpose Registers

64-bit	32-bit	16-bit	8 high bits of lower 16 bits	8-bit	Description
RAX	EAX	AX	AH	AL	Accumulator
RBX	EBX	BX	BH	BL	Base
RCX	ECX	CX	CH	CL	Counter
RDX	EDX	DX	DH	DL	Data (commonly extends the A register)
RBP	EBP	BP		BPL	Base Pointer (meant for stack frames)
R8	R8D	R8W		R8B
R9	R9D	R9W		R9B
R10	R10D	R10W		R10B
R11	R11D	R11W		R11B
R12	R12D	R12W		R12B
R13	R13D	R13W		R13B
R14	R14D	R14W		R14B
R15	R15D	R15W		R15B

Note: you cannot access AH, BH, CH and DH when using the REX.W instruction prefix. This prefix is added (automatically by assemblers) when an operand contains a 64-bit register.

The index registers and stack pointer below can also be used as general-purpose registers.

Index Registers

64-bit	32-bit	16-bit	8-bit	Description
RSI	ESI	SI	SIL	Source Index
RDI	EDI	DI	DIL	Destination Index

Pointer Registers

64-bit	32-bit	16-bit	8-bit	Description
RSP	ESP	SP	SPL	Stack Pointer
RIP	EIP	IP		Instruction Pointer

Note: The instruction pointer can only be used in RIP-relative addressing, which was introduced with long mode.

Segment Registers

16-bit	Description
CS	Code Segment
DS	Data Segment
SS	Stack Segment
ES	Extra Segment (used for string operations)
FS	General-purpose Segment
GS	General-purpose Segment

Segments of CS, DS, ES, and SS are treated as if their base was 0 no matter what the segment descriptors in the GDT say. Exceptions are FS and GS which have MSRs to change their base.

Limit checks are disabled for all segments.

RFLAGS Register

Bit(s)	Label	Description
0	CF	Carry Flag
1	1	Reserved
2	PF	Parity Flag
3	0	Reserved
4	AF	Auxiliary Carry Flag
5	0	Reserved
6	ZF	Zero Flag
7	SF	Sign Flag
8	TF	Trap Flag
9	IF	Interrupt Enable Flag
10	DF	Direction Flag
11	OF	Overflow Flag
12-13	IOPL	I/O Priviledge Level
14	NT	Nested Task
15	0	Reserved
16	RF	Resume Flag
17	VM	Virtual-8086 Mode
18	AC	Alignment Check / Access Control
19	VIF	Virtual Interrupt Flag
20	VIP	Virtual Interrupt Pending
21	ID	ID Flag
22-63	0	Reserved

Control Registers

CR0

bit	label	description
0	pe	protected mode enable
1	mp	monitor co-processor
2	em	emulation
3	ts	task switched
4	et	extension type
5	ne	numeric error
16	wp	write protect
18	am	alignment mask
29	nw	not-write through
30	cd	cache disable
31	pg	paging

CR1

Reserved

CR2

bit	label	description
0-63	pfla	page fault linear address

CR3

bit	description
0-63	physical base address of PML4T

Note that this must be page aligned

CR4

bit	label	description
0	vme	virtual 8086 mode extensions
1	pvi	protected mode virtual interrupts
2	tsd	time stamp disable
3	de	debugging extensions
4	pse	page size extension
5	pae	physical address extension
6	mce	machine check exception
7	pge	page global enable
8	pce	performance monitoring counter enable
9	osfxsr	os support for fxsave and fxrstor instructions
10	osxmmexcpt	os support for unmasked simd floating point exceptions
13	vmxe	virtual machine extensions enable
14	smxe	safer mode extensions enable
17	pcide	pcid enable
18	osxsave	xsave and processor extended states enable
20	smep	supervisor mode executions protection enable
21	smap	supervisor mode access protection enable

CR8

CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).

The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.

System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.

The TPR is cleared to 0 on reset.

Bit	Purpose
0-3	Priority
4-63	Reserved

EFER

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel. Its MSR number is 0xC0000080.

Bit	Label	Description
0	sce	system call extensions
8	lme	long mode enable
10	lma	long mode active
11	nxe	no-execute enable
12	svme	secure virtual machine enable
13	lmsle	long mode segment limit enable
14	ffxsr	fast fxsave/fxrstor
15	tce	translation cache extension

Debug Registers

DR0 - DR3

Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.

DR6

It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.

DR7

bit	description
0	local DR0 breakpoint
1	global DR0 breakpoint
2	local DR1 breakpoint
3	global DR1 breakpoint
4	local DR2 breakpoint
5	global DR2 breakpoint
6	local DR3 breakpoint
7	global DR3 breakpoint
16-17	conditions for DR0
18-19	size of DR0 breakpoint
20-21	conditions for DR1
22-23	size of DR1 breakpoint
24-25	conditions for DR2
26-27	size of DR2 breakpoint
28-29	conditions for DR3
30-31	size of DR3 breakpoint

A local breakpoint bit deactivates on hardware task switches, while a global does not.
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).

Test Registers

name	description
TR3 - TR5	undocumented
TR6	test command register
TR7	test data register

Protected Mode Registers

GDTR

operand size		label	description
64 bit	32 bit
bits 0-15		limit	size of GDT
bits 16-79	bits 16-47	base	starting address of GDT

LDTR

Stores the segment selector of the LDT.

IDTR

operand size		label	description
64 bit	32 bit
bits 0-15		limit	size of IDT
bits 16-79	bits 16-47	base	starting address of IDT