Page history
9 June 2024
10 July 2023
9 June 2022
20 October 2021
osdev>Deadmutex
Added XCR0
+852
osdev>Deadmutex
→CR3
+50
osdev>Deadmutex
→Control Registers: Added CR8
+104
osdev>Deadmutex
→CR4: Added link to Supervisor Memory Protection
+66
13 October 2021
12 October 2021
29 September 2021
osdev>Deadmutex
→CR2: Added bit range for long mode
+5
osdev>Deadmutex
→CR3: Added PWT and PCD bits.
+247
25 December 2020
6 April 2019
11 March 2018
3 March 2018
1 October 2017
16 June 2017
15 June 2017
7 June 2017
osdev>Eladashkcenazi335
→CR5-7
+4
osdev>Eladashkcenazi335
→CR5-7
+5
osdev>Eladashkcenazi335
→CR5-7
osdev>Eladashkcenazi335
→Control Registers
+16
osdev>Eladashkcenazi335
→CR(1, 5->7)
−8
osdev>Eladashkcenazi335
→CR(1,5->7)
+1
osdev>Eladashkcenazi335
→Control Registers
+92
osdev>Eladashkcenazi335
→CR0
+491
9 March 2016
Glauxosdever
no edit summary
+28
Glauxosdever
no edit summary
−28
Glauxosdever
no edit summary
+9
Glauxosdever
no edit summary
−9
Glauxosdever
Add the page into the CPU_Registers category
+28
10 January 2016
15 December 2015
6 December 2015
2 May 2015
osdev>Glauxosdev
Segment Registers ~> Protected Mode Registers (wrong caption)
m+7
Roman
no edit summary
−8
Roman
→General purpose registers
1 May 2015
30 April 2015
osdev>Glauxosdev
Fill LDTR based on the x86-64 article.
m+39
osdev>Glauxosdev
Tablify DR7
+182
osdev>Glauxosdev
no edit summary
+34
osdev>Glauxosdev
moved CPU Register x86 to CPU Registers x86: Consistency with CPU Registers x86-64
m