CPU Registers x86: Difference between revisions

Jump to navigation Jump to search
[unchecked revision][unchecked revision]
Line 295:
| Page-level Write-Through
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 4
Line 301:
| Page-level Cache Disable
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 12-31 (63)
Line 307:
| Page Directory Base Register
| Base of PDPT
| Base of PML4T/PML5T
|-
|}
Anonymous user
Cookies help us deliver our services. By using our services, you agree to our use of cookies.

Navigation menu