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CPU Registers x86: Difference between revisions
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Tablify DR7
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(Tablify DR7) |
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Line 353:
====DR6====
It permits the debugger to determine which debug conditions have
====DR7====
{| {{wikitable}}
|-
! bit
! description
|-
| 0
| local DR0 breakpoint
|-
| 1
| global DR0 breakpoint
|-
| 2
| local DR1 breakpoint
|-
| 3
| global DR1 breakpoint
|-
| 4
| local DR2 breakpoint
|-
| 5
| global DR2 breakpoint
|-
| 6
| local DR3 breakpoint
|-
| 7
| global DR3 breakpoint
|-
| 16-17
| conditions for DR0
|-
| 18-19
| size of DR0 breakpoint
|-
| 20-21
| conditions for DR1
|-
| 22-23
| size of DR1 breakpoint
|-
| 24-25
| conditions for DR2
|-
| 26-27
| size of DR2 breakpoint
|-
| 28-29
| conditions for DR3
|-
| 30-31
| size of DR3 breakpoint
|-
|}
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).
==Test registers==
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