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ARMv7 Generic Timers: Difference between revisions
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= Overview =
The ARM Generic Timers (henceforth, "GT") are architecturally specified in ARMv7 as an <tt>OPTIONAL</tt> extension to the ARMv7-a and ARMv7-r streams. The feature is specified to provide a system-wide timestamp-counter (
This upcounter can be read in two forms, and these readout-forms are logically distinct from the actual value of the syscounter (though the physcounter will usually reflect the syscounter exactly):
* Physical upcounter readout ("
* Virtual upcounter readout ("
The feature also specifies a set of 4 timers per CPU which base their operation on these two upcounters:
* Secure
* Non-secure
* Hypervisor timer
* Virtual timer
= System counters =
The GT's
* At least 56 bits wide. Any read from the
* The
* Supports clock multiplication to save power. I.e, the hardware crystal may operate at a lower frequency than the frequency claimed by the platform, and a multiplier may applied to the readout value to present the illusion of operation at a higher frequency. The underlying crystal's frequency may change dynamically at runtime.
* Roll-over time is guaranteed to be at least 40 years.
* Clock drift is not required to be at any level of accuracy, but ARM <tt>RECOMMENDS</tt> that drift be not greater than 10 seconds per 24 hours. The use of clock multiplication must not change the drift behaviour of the
* The
* The
All agents (including devices in the system other than the host processors) reading the
== Registers ==
The <tt>CNTFREQ</tt> register is only ''writeable'' by ''secure'' PL1 mode software, and must be initialized to state the frequency of the system upcounter.▼
The control registers for the system counter are not accessible as coprocessor interface registers, and are only accessible through a memory mapped interface. The controls include enabling/disabling the syscounter, setting the syscounter's value, changing the syscounter's frequency and multiplier, and enabling/disabling halt-on-debug, so that a debugger can halt the syscounter when a processor enters halting debug-mode.
The physical and virtual upcounters as well as the timer registers are architecturally configurable.
=== CNTKCTL ===
Enables PL1 software to control access to the counters and timers from PL0 modes.
* Bits PL0PCTEN and PL0VCTEN enable/disable access to <tt>CNTVCT</tt>, <tt>CNTPCT</tt> and <tt>CNTFREQ</tt> from PL0 modes.
* Bit PL0PTEN enables/disables access to <tt>CNTP_CTL</tt>, <tt>CNTP_CVAL</tt> and <tt>CNTP_TVAL</tt> from PL0 modes.
* Bit PL0VTEN enables/disables access to <tt>CNTV_CTL</tt>, <tt>CNTV_CVAL</tt> and <tt>CNTV_TVAL</tt> from PL0 modes.
* Bits EVENTEN, EVENTDIR and EVENTI enable and control the direction and bit-position of the bit that triggers the events generated by the virtual counter (CNTVCT).
=== CNTHCTL ===
Enables PL2 software to control access to the counters and timers from non-secure PL1 and PL0 modes.
* Bit PL1PCTEN enables/disables access to CNTPCT from non-secure PL1 and PL0 modes.
* PL1PCEN enables/disables access to the phyisical timer registers (CNTP_CTL, CNTP_TVAL, CNTP_CVAL) from non-secure PL1 and PL0 mode.
=== CNTFREQ ===
▲The <tt>CNTFREQ</tt> register is only ''writeable'' by ''secure'' PL1 mode software, and must be initialized to state the frequency of the system upcounter, '''in Hz'''.
<tt>CNTFREQ</tt> is ''readable'' by PL2, secure and non-secure PL1 by default. <tt>CNTKCTL.PL0PCTEN</tt> enables <tt>CNTFREQ</tt> to be read from secure and non-secure PL0.
=== CNTPCT ===
* Is always accessible from PL2.
* Is always accessible from PL1 modes. However, if hypervisor extensions are supported accesses to CNTPCT will generate a hyp-trap from PL1 unless CNTHCTL.PL1PCTEN is set to 1.
* Is only accessible from PL0 modes if CNTKCTL.PL0CTEN is set to 1. If CNTKCTL.PL0CTEN
= Timers =
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*
== Registers ==
== CNTFREQ ==
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