RISC-V
RISC-V is not a single ISA, rather a meta-ISA. It defines basics and boundaries for a family of implementations. The specification is published under a Creative Commons License and actively developed on Github. RISC-V seeks to address two problems with developing hardware processors: copyright (such as Arm's) hampering educational and hobbyist processors, and the historical baggage associated with some architectures (such as x86) making those architectures unwieldy to manufacture and design around.
An implementation consists of one of the Base ISAs and zero or more Extensions.
Architecture
The RISC-V ISA has fixed-length 32-bit instructions aligned on their natural boundaries, but is designed to encode variable-length instructions.
The base ISA operates on a little-endian memory system, but non-standard extensions may add support for big-endian or bi-endian.
Hardware Threads
The RISC-V ISA specifies hardware threads, called harts. A hart has its own state and serves as RISC-V's term for a logical CPU core. A processor may contain multiple harts and has at least one. Each hart has an ID associated with it and at least one hart has ID 0.
Exceptions, Traps and Interrupts
In RISC-V the term Exception refers to an unusual condition at run-time associated with an instruction in the current hardware thread.
A Trap is a synchronous transfer of control to a trap handler and is caused by an exceptional condition within a RISC-V thread. The trap handlers usually execute in a more privileged environment.
An external event that occurs asynchronously to the current thread will cause an Interrupt. When an interrupt occurs, the currently running instruction(s) finish or are cancelled and the CPU executes the interrupt handler.
Privileges
The spec defines a debug mode and 4 privilege modes, of which a valid combination has to be implemented. The modes are:
| Debug | Mode for complete control, for debuggers |
| Machine | Mode with nearly full control, no debug registers (think firmware), not optional |
| Hypervisor | VM-Hypervisor |
| Supervisor | OS-level |
| User | Application-level, lowest privilege |
Possible Combinations
Valid combinations of privilege levels are:
- One level: Machine mode only for embedded systems
- Two levels: Machine and User mode, small systems
- Three levels: Machine, Supervisor and User mode, complex systems able to run Unix-like operating systems
- Four levels: Machine, Hypervisor, Virtual supervisor and User mode, complex systems supporting virtualization in hardware
Changing privilege
In RISC-V, the privilege mode of a hart can be changed by:
- A trap or interrupt in the thread caught by a higher privilege mode
- The execution of the
mretorsretinstructions - Intervention by a hardware debugger
- A hart being reset (it always starts in Machine mode)
When a trap or interrupt occurs, the hart determines which privilege mode will catch this exception and jump to the address stored in mtvec or stvec, possibly with an offset, for exceptions caught by Machine and Supervisor mode respectively. This mode with an offset into an interrupt vector table is called vectored interrupts. RISC-V traps do not use an offset. This has the side effect of making the interrupt vector table a table of jump instructions as opposed to a table of addresses.
The mret and sret instructions update the privilege mode to that specified by mstatus or sstatus respectively before resuming in said mode at the address stored in mepc or sepc respectively. These instructions are intended for returning from trap/interrupt handlers and explicit privilege mode switches.
Base ISA
The base ISA specifies RV32I and RV64I, 32 and 64-bit respectively; most of what is said about RV32I also applies to RV64I. Additionally, there is also RV32E, a reduced version of RV32I for embedded systems, and RV128I, a 128-bit version, which is mostly a placeholder so far.
RV32I
RV32I offers 31 general-purpose registers (x1-x31) which hold integer values, while the x0 register is hardwired to zero; all registers are 32 bits wide. It specifies a number of logical and arithmetic operations (and, or, xor, shift left and right, addition and subtraction), all of which are available with a source register or an immediate.
RV32E
RV32E reduces the number of general-purpose registers to 15 (x1-x15), and x0 is still hardwired to constant zero.
RV64I
RV64I is very similar to its 32-bit counterpart, but offers 64-bit wide registers and can read the CSRs in one operation instead of requiring the programmer to read the upper and lower half separately. Additionally, there are some instructions to work with words (32 bit) instead of double-words.
RV128I
Like RV64I but with 128bit register length. This base ISA is not ratified and no widely adopted CPUs that support RV128I exist.
Extensions
An extension can be one of the officially defined ones or a vendor-specific one (there is opcode space explicitly reserved for this) and can define additional elements, including opcodes and registers.
The following Standard Extensions are noteworthy here:
Zicsr
This extensions defines some kind of secondary address space for Control and Status Register, which is used for controlling things like interrupts, privilege level, hart-local timers and such. These registers can be accessed via the CSR instructions.
RVM (Multiply-Divide Instruction Extension)
The RVM Extension adds instructions for multiplying, dividing and computing the remainder of a division.
RVA (Atomic Instruction Extension)
The RVA Extension adds instruction to work atomically with memory, including reserved load and conditional store.
RVF & RVD & RVQ (Floating Point Extensions)
Adds additional instructions to work with floating points and also the floating point registers. The different extensions differ in the length/precision of the floating point numbers. The extensions F, D and Q are for single, double and quad precision respectively.
RVV (Vector Instruction Extension)
The RISC-V V extension adds a vector register file and instructions for operating on vectors. Note that RISC-V's vectors have a very different model from e.g. x86 in that a vector register's width is an implementation detail of the hart instead of an ISA-mandated specific size. These vector instructions conceptually work more like a stream of operations rather than operating on a predetermined amount of values in batches. Be warned that there are differences between RVV versions 0.7 and 1.0 which may break some software.
C (Compressed Instructions Extension)
Allows 16-bit variants of common instructions with a reduced register set (16 instead of 32) and is intended to increase code density. It can be freely mixed with 32-bit instructions. Note that this also has the effect of relaxing the alignment of 32-bit instructions to a 16-bit boundary.
Running RISC-V
Emulator, Simulators, etc
For advanced setups (multiple privilege modes, etc.), QEMU is probably the way to go. Other simulators exist, but the author has not yet tried them :-)
Real Hardware
Some fairly inexpensive SoCs are becoming available, notably VisionFive 2 from StartFive [1] and Star64 form Pine64 [2]. Both of these are Raspberry Pi like devices based on JH7110 Quad-Core SiFive U74 64-Bit CPU with MMU, GPU, GPIO, Ethernet, et al and run Linux.
Also note HiFive Unleashed, which is also able to run Linux, has multiple cores, and is expandable.
The PolarFire SoC Icicle Kit [3] by Microchip also contains cores by SiFive and can run Linux, but is cheaper than the HiFive Unleashed.
Most other hardware implementations (which are for sale for normal consumers) are more in the category of "microcontrollers" and lack parts like a Memory Management Unit (MMU), I/O for humans (keyboard, graphics, sound), etc.
The Kendryte K210 (e.g. in the MAIX Bit-board) is a RV64IMACFD_Zicsr_Zifence processor with two harts and quite cheap.