Category:RISC-V: Difference between revisions
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[http://www.riscv.org/ RISC-V] is a completely free and open ISA designed by the [http://www.riscv.org/risc-v-foundation/ RISC-V Foundation] at the EECS departement at the University of California, Berkley.<br/> |
[http://www.riscv.org/ RISC-V] is a completely free and open ISA designed by the [http://www.riscv.org/risc-v-foundation/ RISC-V Foundation] at the EECS departement at the University of California, Berkley.<br/> |
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It was designed to be simple and directly implementable in real hardware, and consists of a base integer ISA, called RV32I or RV64I for 32 and 64-bit respectivly, it also provides additional standard extensions, as well as room for non-standard (e.g. community/user specified) ones. |
It was designed to be simple and directly implementable in real hardware, and consists of a base integer ISA, called RV32I or RV64I for 32 and 64-bit respectivly, it also provides additional standard extensions, as well as room for non-standard (e.g. community/user specified) ones. |
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[[Category:Platforms]] |
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Latest revision as of 15:05, 24 February 2017
RISC-V is a completely free and open ISA designed by the RISC-V Foundation at the EECS departement at the University of California, Berkley.
It was designed to be simple and directly implementable in real hardware, and consists of a base integer ISA, called RV32I or RV64I for 32 and 64-bit respectivly, it also provides additional standard extensions, as well as room for non-standard (e.g. community/user specified) ones.
Pages in category "RISC-V"
The following 5 pages are in this category, out of 5 total.