972
edits
[unchecked revision] | [unchecked revision] |
m (Fixed wrong CPUID bit for AVX2, added some informations about detecting AVX512.) |
m (Bot: Replace deprecated source tag with syntaxhighlight) |
||
Line 44:
Example usage:
<
char fxsave_region[512] __attribute__((aligned(16)));
asm volatile(" fxsave %0 "::"m"(fxsave_region));
</syntaxhighlight>
or in asm:
<
segment .code
SaveFloats:
Line 56:
align 16
SavedFloats: TIMES 512 db 0
</syntaxhighlight>
Pitfalls: only one level of saving supported.
Line 117:
Here is an example of assembly code enabling AVX after SSE has been enabled (you should check AVX and XSAVE are supported first, see above):
<
enable_avx:
push rax
Line 132:
pop rax
ret
</syntaxhighlight>
To enable AVX-512, set the OPMASK (bit 5), ZMM_Hi256 (bit 6), Hi16_ZMM (bit 7) of XCR0. You must ensure that these bits are valid first (see above).
|