APIC: Difference between revisions

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Added logical addressing mode information and link to useful book
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m (Replaced broken link to APIC tutorial with archived version)
(Added logical addressing mode information and link to useful book)
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| Bits 56-63
| Destination field. If the destination mode bit was clear, then the lower 4 bits contain the bit APIC ID to sent the interrupt to. If the bit was set, the upper 4 bits also contain a set of processors. (TODO:See The manual is very vague about this mode - find out what this meansbelow).
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For more information, check out chapter 3 of http://download.intel.com/design/chipsets/datashts/29056601.pdf.
 
== Logical Destination Mode ==
Logical destination mode uses an 8-bit logical APIC ID, contained in the LDR (logical destination register, unique to each APIC). All APICs compare their local ID to the destination code sent with the interrupt. This allows to target a group of processors by programming them with the same logical APIC ID.
 
The LDR is formatted as follows
{| class="wikitable"
|-
| Bits 0-23
| Reserved.
|-
| rowspan="3" | Bits 24-31
| Flat model
| Bitmap of target processors (bit identifies single processor; supports a maximum of 8 local APIC units)
|-
| rowspan="2" | Cluster model
| Bits 24-27
| Local APIC address (identifies the specific processor in a group)
|-
| Bits 28-31
| Cluster address (identifies a group of processors)
|}
 
The DFR (destination format register) specifies Flat or Cluster model and is structured as follows
{| class="wikitable"
|-
| Bits 0-27
| Reserved.
|-
| Bits 28-31
| Model (1111b = Flat model, 0000b = Cluster model)
|}
 
More info can be found in [https://books.google.nl/books?id=TVzjEZg1--YC&printsec=frontcover "Pentium Processor System Architecture. Chapter 15: The APIC"]
 
== See Also ==
Line 210 ⟶ 243:
* [https://web.archive.org/web/20140308064246/http://www.osdever.net/tutorials/pdf/apic.pdf Advanced Programmable Interrupt Controller by Mike Rieker]
* [https://web.archive.org/web/20100918084750/http://www.microsoft.com/whdc/archive/apic.mspx "The Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs". Microsoft. 18 September 2010]
* [https://books.google.nl/books?id=TVzjEZg1--YC&printsec=frontcover Pentium Processor System Architecture]
 
[[Category:Interrupts]]
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