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SSE: Difference between revisions
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Added information on AVX-512
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(Merging AVX page into SSE page, as it was already mentioned here) |
(Added information on AVX-512) |
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The bit for CVT16 can be found on CPUID page 1, in ECX bit 29
======AVX======
The bit for AVX can be found on CPUID page 1, in ECX bit 28
======XSAVE======
The bit for XSAVE (needed to manage extended processor states) can be found on CPUID page 1, in ECX bit 26
=====AVX-512=====
The bits for AVX-512 are in CPUID page 0x0D, 0x0, EAX bits 5-7
===X86_64===
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=== AVX ===
AVX
Both SSE and OSXSAVE must be enabled before allowing. Failing to do so will also produce an #UD.
AVX is enabled by setting bit 2 of the XCR0 register. Bit 1 of XCR0 must also be set (indicating SSE support).
Here is an example of assembly code enabling AVX after SSE has been enabled (you should check AVX
<source lang="asm">
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</source>
To enable AVX-512, set the OPMASK (bit 5), ZMM_Hi256 (bit 6), Hi16_ZMM (bit 7) of XCR0. You must ensure that these bits are valid first (see above).
==See Also==
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