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SSE: Difference between revisions
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Merging AVX page into SSE page, as it was already mentioned here
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== Updates to SSE ==
Later processors have added more instructions for different work to be performed on the vector registers. Supporting them with SSE support in place doesn't require any effort on the part of the OS (except for AVX, see below). The actual user of the instructions should however check if those instructions actually exist.
=== CPUID bits ===
=====SSE2=====
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When the [[X86-64]] architecture was introduced, AMD demanded a minimum level of SSE support to simplify OS code. Any system capable of long mode should support at least SSE and SSE2, which means that the kernel does not need to care about the old FPU save code.
X86-64 adds 8 SSE registers (xmm8 - xmm15) to the mix. However, you can only access these in 64 bit mode.
'''Advanced Vector Extensions''' is a '''SIMD''' (Single Instruction, Multiple Data) instruction set introduced by Intel in 2011.
=== AVX ===
AVX need to be enabled by the kernel before being used. Forgetting to do this will raise an #UD on the first AVX call.
Both SSE and OSXSAVE must be enabled before allowing. Failing to do so will also produce an #UD.
AVX is enabled by setting bit 2 of the XCR0 register. Bit 1 of XCR0 must also be set (indicating SSE support).
Here is an example of assembly code enabling AVX after SSE has been enabled (you should check AVX is supported first, see above):
<source lang="asm">
enable_avx:
push rax
push rcx
xor rcx, rcx
xgetbv ;Load XCR0 register
or eax, 7 ;Set AVX, SSE, X87 bits
xsetbv ;Save back to XCR0
pop rcx
pop rax
ret
</source>
==See Also==
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