X86-64
This article discusses x86-64 CPUs (AMD64 and Intel's equivalent EM64T implementation). IA-64 (Itanium) is really a different beast and not addressed here.
Features
What does Long Mode offer?
Long mode extends general registers to 64 bits (RAX, RBX, RIP, RSP, RFLAGS, etc), and adds an additional 8 integer registers (R8, R9, ..., R15) plus 8 more SSE registers (XMM8 to XMM15) to the CPU. Linear addresses are extended to 64 bit (however, a given CPU may implement less than this) and the physical address space is extended to 52 bits (a given CPU may implement less than this). In essence long mode adds another mode to the CPU:
- Real mode
- Legacy mode (32 bit protected mode)
- Long mode (64 bit protected mode)
- System Management mode
Long mode does not support hardware task switching or virtual 8086 tasks, and most of the segment register details are ignored (a flat memory model is required). In long mode the current CS determines if the code currently running is 64 bit code (true long mode) or 32 bit code (compatibility mode), or even 16-bit protected mode code (still in compatibility mode).
The first 64 bit CPUs from both Intel and AMD support 40 bit physical addresses and 48 bit linear addresses.
Segmentation in Long Mode
Segmentation in long mode functions with a flat model with the exception of two registers: FS and GS. Setting the base address for these two segment registers is possible via two specific MSRs, FS.base (C000_0100h)and GS.base (C000_0101h).
Additionally there is a long mode specific instruction called SWAPGS, which swaps the contents of GS.base and another MSR called KernelGSBase (C000_0102h). This instruction is particularly useful for preserving kernel information for a specific logical processor core across context switches. Note: This is an exchange operation.
Lastly it also important to note that any attempt to load a selector value into the FS or GS registers in long mode will automatically set their base addresses to zero due to the previously mentioned semantics of long mode segmentation.
Setting up
How do I detect if the CPU is 64 bits ?
You can find that out by checking CPUID. All AMD64 compliant processors have the longmode-capable-bit turned on in the extended feature flags (bit 29) in EDX, after calling CPUID with EAX=0x80000001. There are also other bits required by long mode, but you can see those yourself in CPUID at AMD general purpose instruction reference
How do I enable Long Mode ?
The steps for enabling long mode are:
* Have paging disabled * Set the PAE enable bit in CR4 * Load CR3 with the physical address of the PML4 * Enable long mode by setting the EFER.LME flag in MSR 0xC0000080 * Enable paging
Now the CPU will be in compatibility mode, and instructions are still 32-bit. To enter long mode, the D/B bit (bit 22, 2nd dword) of the GDT code segment must be clear (as it would be for a 16-bit code segment), and the L bit (bit 21, 2nd dword) of the GDT code segment must be set. Once that is done, the CPU is in 64-bit long mode.
Are there restrictions on 32-bit code running in Legacy Mode ?
x86-64 processors can operate in a legacy mode, they still start in real mode and protected mode is still available (along with the associated v8086 mode). This means an x86 operating system, even DOS, will still run just fine. The only difference is that physical addresses can be up to 52 bits (or as many bits as implemented by the CPU) when PAE is used.
However, there is nothing like Virtual 8086 Mode (16 bits support) once in long/compatibility mode.
Entering Long Mode directly
Protected mode must be entered before activating long mode. A minimal protected-mode environment must be established to allow long-mode initialization to take place. This environment must include the following:
- A protected-mode IDT for vectoring interrupts and exceptions to the appropriate handlers while in protected mode.
- The protected-mode interrupt and exception handlers referenced by the IDT.
- Gate descriptors for each handler must be loaded in the IDT.
- --AMD64 docs, volume 2, section 14.4 (Enabling Protected Mode), 24593 Rev. 3.10 February 2005
That being said, we have a thread where Brendan shows how you can enable 64-bit long mode with no 32-bit IDT and no 32-bit segments ... Be assured, however, that any paging-related exception that occurs in long mode before you enable 64-bit IDT will cause the processor to reset due to a triple fault ... There is also an example of this implemented in a bootloader.
64bit Environment Models
The following discusses issues related to data types of high level languages. So, it's not relevant for people developing only in assembly.
There are three 64bit programming models you need to consider: LP64, ILP64, LLP64. Each model has its own pitfalls. The I/L/P stand for Int, Long, Pointer, respectively; and the 64 means thats how many bits in each.
This LP64 means Longs and Pointers are 64bits wide. LL is a special case and means long-long...
Data Types
This table lists the breakdown of sizes in the various programming models.
| Datatype | LP64 | ILP64 | LLP64 | ILP32 | LP32 |
|---|---|---|---|---|---|
| char | 8 | 8 | 8 | 8 | 8 |
| short | 16 | 16 | 16 | 16 | 16 |
| _int | 32 | -- | 32 | -- | -- |
| int | 32 | 64 | 32 | 32 | 16 |
| long | 64 | 64 | 32 | 32 | 32 |
| long long | -- | -- | 64 | -- | -- |
| pointer | 64 | 64 | 64 | 32 | 32 |
Models used by 64bit OSs
The following table lists what some current 64bit OS have as a programming model.
| OS | Mode |
|---|---|
| Windows XP X64 | LLP64 |
| Linux | LP64 |
| Solaris | LP64 |
| DEC OSF/1 Alpha | LP64 |
| SGI Irix | LP64 |
| HP UX 11 | LP64 |