VGA Hardware: Difference between revisions

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fixed 16-color mode bit ordering
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updated info headers, filled in CRTC timing info.
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{{In Progress}}

I'm working on the [[VGA Hardware]] page, doing it here so my chaos doesnt bloat the wiki as of yet. In the end I hope it will enable newbs to write video drivers without using BIOS, v8086 or anything - [[User:Combuster|Combuster]] 05:46, 19 December 2006 (CST)
I'm working on the [[VGA Hardware]] page, doing it here so my chaos doesnt bloat the wiki as of yet. In the end I hope it will enable newbs to write video drivers without using BIOS, v8086 or anything - [[User:Combuster|Combuster]] 05:46, 19 December 2006 (CST)


Since thorough documentation is scarce I can only try to reverse engineer behaviour on various systems. I check with Bochs, Qemu, VPC, and once in a while, both video cards in this computer (ati x300 and gf6). Ill try to list differences as good as possible. If somebody has a original IBM VGA, please let me know and i'll spam you :). Other test beds are of course also welcome although i do have a nice range of cards already at my disposal. - [[User:Combuster|Combuster]] 07:58, 19 December 2006 (CST)


Things i'm currently going after:
Things that still need to be done:
* I need to reverse engineer documentation for the sequencer.
* running probes on the GC mechanics (which seem to horribly differ between hosts. I sure hope nvidia and ati are mutually consistent)
* I need to test some additional GC bits for effects.
* creating diagrams of hardware
* Read Modes 0 and 1, Write modes 1,2,3 (this is easy as this documentation is rather complete. I Have not tested all details of this stuff)
* Register Accessing (pretty obvious for the insider, although i recently caught a guru messing this up O.o)
* Color Logic (There's more to this than the eye meets. I can write this from info out of Abrash's book, but i should still test it anyway
* CRTC: byte word doubleword mode, doublescanning, why 256-color modes have halved horizontal resolutions. Some of this depends on the sequencer operation...
- [[User:Combuster|Combuster]] 16:55, 27 December 2006 (CST)



What you can do:
* Proof-read it, check for sanity.
* Comment on n00b-friendliness
* check registers and timings
* probably a lot more :)
- [[User:Combuster|Combuster]] 16:55, 27 December 2006 (CST)




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----

{{In Progress}}


The VGA is a complex piece of hardware. Even though its old, many modern graphics cards are compatible with it, including NVidia and ATI cards. This can make writing an VGA driver rather attractive. The amount of compatibility varies however, and do not ever assume a compatible card without proper hardware detection.
The VGA is a complex piece of hardware. Even though its old, many modern graphics cards are compatible with it, including NVidia and ATI cards. This can make writing an VGA driver rather attractive. The amount of compatibility varies however, and do not ever assume a compatible card without proper hardware detection.
Apart from real machines, several emulators and virtual machines provide VGA emulation, including [[Bochs]], [[QEMU]] and [[Microsoft Virtual PC]]
Apart from real machines, several emulators and virtual machines provide VGA emulation, including [[Bochs]], [[QEMU]] and [[Microsoft Virtual PC]]

'''WARNING: Improperly changing CRTC settings can be harmful to the monitor attached to it'''

'''DISCLAIMER: The information provided might not be accurate, and using them is to be done entirely at your own risk'''




== Overview ==
== Overview ==
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== Video Memory Layout ==
== Video Memory Layout ==
The video memory consists of four 'planes' (individual units) of memory, each with a size of 64KB, giving the VGA 256k of video memory. Connected to it is the Sequencer, which interprets this memory to generate colors which are fed to the subsequent stages. The way colors are organized in this memory mainly depends on the color depth.
The video memory consists of four 'planes' (individual units) of memory, each with a size of 64KB, giving the VGA 256k of video memory. Connected to it is the Sequencer, which interprets this memory to generate colors which are fed to the subsequent stages. The way colors are organized in this memory mainly depends on the color depth.


=== Memory Layout in 16-color graphics modes ===
=== Memory Layout in 16-color graphics modes ===
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''' Todo: write modes, read modes '''
''' Todo: more write modes, read modes '''


== The Sequencer ==
== The Sequencer ==
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== The CRT Controller ==
== The CRT Controller ==
The Cathode Ray Tube Controller, or CRTC, is the unit to create a video signal from the data produced by the DAC. By programming this unit you can control the resolution of your monitor, as well as some hardware overlay and panning effects.
The Cathode Ray Tube Controller, or CRTC, is the unit to create a video signal from the data produced by the DAC. By programming this unit you can control the resolution of your monitor, as well as some hardware overlay and panning effects.

'''WARNING: Improperly changing CRTC settings can be harmful to the monitor attached to it'''


The following diagram gives a quick overview of how the CRTC is generally configured (with register names)
The following diagram gives a quick overview of how the CRTC is generally configured (with register names)

=== Resolution and Timing ===


[[Image:VGA crtc.gif|CRTC output diagram]]
[[Image:VGA crtc.gif|CRTC output diagram]]
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Horizontal timigs are based on character clocks (multiples of 8 or 9 pixels), Vertical timings are per-scanline. Since these easily exceed the 255 limit of one byte, the Overflow Register is used to store the high-order bits.
Horizontal timigs are based on character clocks (multiples of 8 or 9 pixels), Vertical timings are per-scanline. Since these easily exceed the 255 limit of one byte, the Overflow Register is used to store the high-order bits.


Horizontally and vertically, the area can be separated into four parts:
'''TODO: Add more programming related information'''
* Active Display: The data rendered from memory, from the human perspective this area equals the resolution.
* Overscan: the area around the Active Display. Although commonly black, this can be made visible by changing its colour. By default this is 8 pixels in size on each end.
* Blanking Area: When the CRTC disables the colour output. This is the black area around the screen. By changing this you can move, center, and scale the screen.
* Retrace Period: This area is not generally visible. This is just a signal sent to the monitor to go to the next scanline or the next frame. However, monitors may steal some of this time for the blanking area following it or vice versa. Consequently, the blanking sizes on either side are not equal to accomodate.

==== Registers ====
Registers involved in horizontal timing:
{| {{Wikitable}}
|-
! Register Name
! Port
! Index
! 7
! 6
! 5
! 4
! 3
! 2
! 1
! 0
|-
| Horizontal Total Register
| 0x3D4
| 0x00
| colspan="8" | Horizontal Total
|-
| End Horizontal Display Register
| 0x3D4
| 0x01
| colspan="8" | Horizontal Display End
|-
| Start Horizontal Blanking Register
| 0x3D4
| 0x02
| colspan="8" | Horizontal Blanking Start
|-
| End Horizontal Blanking Register
| 0x3D4
| 0x03
|
| colspan="2" | Horizontal Display Skew
| colspan="5" | Horizontal Blanking End (bits 0..4)
|-
| Start Horizontal Retrace Register
| 0x3D4
| 0x04
| colspan="8" | Horizontal Retrace Start
|-
| End Horizontal Retrace Register
| 0x3D4
| 0x05
| H. Blanking End (bit 5)
| colspan="2" |
| colspan="5" | Horizontal Retrace End
|}

Registers involved in vertical timing:
{| {{Wikitable}}
|-
! Register Name
! Port
! Index
! 7
! 6
! 5
! 4
! 3
! 2
! 1
! 0
|-
| Vertical Total Register
| 0x3D4
| 0x06
| colspan="8" | Vertical Total (bits 0..7)
|-
| Overflow Register
| 0x3D4
| 0x07
| V.Retr.St. (9)
| V.Disp.End (9)
| V.Total (9)
|
| V.Blank.St. (8)
| V.Retr.St. (8)
| V.Disp.End (8)
| V.Total (8)
|-
| Maximum Scan Line Register
| 0x3D4
| 0x09
| colspan="2" |
| V.Blank.St. (9)
| colspan="5" |
|-
| Vertical Retrace Start Register
| 0x3D4
| 0x10
| colspan="8" | Vertical Retrace Start (bits 0..7)
|-
| Vertical Retrace End Register
| 0x3D4
| 0x11
| colspan="4" |
| colspan="4" | Vertical Retrace End
|-
| Vertical Display End Register
| 0x3D4
| 0x12
| colspan="8" | Vertical Display End (bits 0..7)
|-
| Vertical Blanking Start Register
| 0x3D4
| 0x15
| colspan="8" | Vertical Blanking Start (bits 0..7)
|-
| Vertical Blanking End Register
| 0x3D4
| 0x16
| colspan="8" | Vertical Blanking End (bits 0..6)
|}

Other registers dealing with timing:
{| {{Wikitable}}
|-
! Register Name
! Port
! Index
! 7
! 6
! 5
! 4
! 3
! 2
! 1
! 0
|-
| Miscellaneous Output Register
| 0x3C2
| -
| colspan="4" |
| colspan="2" | Clock Select
| colspan="2" |
|-
| Clocking Mode Register
| 0x3C4
| 0x01
| colspan="7" |
| colspan="2" | 9/8 Dot Mode
|}

==== Timing Model ====

The horizontal timing registers are based on a unit called 'character' (As they match one character in text mode). Each character equals 8 ('''9/8 Dot Mode''' is set) or 9 ('''9/8 Dot Mode''' is clear) pixels. Each scanline contains '''Horizontal Total''' + 5 characters, zero based. '''Horizontal Display End''' tells us the last character that is calculated from memory (i.e. the horizontal resolution in characters minus one). '''Horizontal Blanking Start''' and '''Horizontal Retrace Start''' give us the the last character before either period is started. '''Horizontal Blanking End''' and '''Horizontal Retrace End''' need more explanation, as they only contain part of a number. When blanking or horizontal retrace is enabled the significant bits are checked against the character counter, and if these bits match the respective period will be ended. The quick solution is to calculate the appropriate values, compute the last character clock at which each period should be active, then AND it with 0x3F (Blank) or 0x1F (Retrace) to get the register's value. Note that the periods must be between 1 and 63(Blank)/31(Retrace) character clocks. To be safe, there must be at least one character of overscan on each side of the screen to avoid additional artefacts.

The vertical timing is similar, apart from the fact that these registers operate on scan lines (pixels) instead of characters. The '''Vertical Retrace End''' and '''Vertical Blank End''' registers work also similar, although they are different sizes. The Retrace End is 4 bits wide (AND with 0xF, period is 1-15 scanlines), The Blank End size is at least 7 bits (some say its 8, some say its 7), so the value is computed by ANDing with 0xFF, with the period ranging from 1-127 scanlines. As with horizontal timing, at least one scan line of overscan must be present to avoid possible artefacts.

The clock can be selected using '''Clock Select'''. Only two of four possible clocks are present on all VGAs. A clock of 25MHz is selected when this field is zero, 28MHz is selected when this field equals 1. Some boards have other clocks under values 2 and 3, but you should not write these values unless you know the clock that is there. Note that selecting the 28MHz clock and 9 pixels per pixel results in the same timings as selecting the 25MHz clock and 8 pixels per character, only with different resolutions.

The refresh rates can be calculated as follows:
* Horizontal Refresh Rate = Clock Frequency (in Hz) / total pixels horizontally
* Vertical Refresh Rate = Horizontal Refresh Rate / total scan lines
On a VGA monitor, the horizontal refresh rate should equal 31.25 kHz. Vertically, only 400 and 480 pixel resolutions are used.

If your monitor supports it, you can set virtually any crazy resolution you want. (provided the horizontal resolution is a multiple of 8 or 9 - 8 seems to be common) Most modern monitors allow anything between 400x300 and 800x600 being set this way.

==== Sample timing scheme ====

640x480 (16 bits) uses the following sizes:
* Timing: 25MHz dot clock, 8 pixels per character
* Totals: 800 pixels horizontally, (100 characters), 524 scan lines
* Active Display: 640x480 (80 characters, 480 scan lines)
* Overscan: 8 pixels (8 scan lines vertically / 1 character clock horizontally) on each side
* Horizontal Retrace: 12 characters (96 pixels)
* Vertical Retrace: 2 scan lines
* Blanking (Left): 2 characters (16 pixels)
* Blanking (Right): 4 characters (32 pixels)
* Blanking (Top): 24 scan lines
* Blanking (Bottom): 2 scan lines
Which should be VGA compatible


[[Category:Stubs]]
[[Category:Stubs]]
[[Category:VGA]]