VGA Hardware
I'm working on the VGA Hardware page, doing it here so my chaos doesnt bloat the wiki as of yet. In the end I hope it will enable newbs to write video drivers without using BIOS, v8086 or anything - Combuster 05:46, 19 December 2006 (CST)
Since thorough documentation is scarce I can only try to reverse engineer behaviour on various systems. I check with Bochs, Qemu, VPC, and once in a while, both video cards in this computer (ati x300 and gf6). Ill try to list differences as good as possible. If somebody has a original IBM VGA, please let me know and i'll spam you :). Other test beds are of course also welcome although i do have a nice range of cards already at my disposal. - Combuster 07:58, 19 December 2006 (CST)
Things i'm currently going after:
- running probes on the GC mechanics (which seem to horribly differ between hosts. I sure hope nvidia and ati are mutually consistent)
- creating diagrams of hardware
The VGA is a complex piece of hardware. Even though its old, many modern graphics cards are compatible with it, including NVidia and ATI cards. This can make writing an VGA driver rather attractive. The amount of compatibility varies however, and do not ever assume a compatible card without proper hardware detection. Apart from real machines, several emulators and virtual machines provide VGA emulation, including Bochs, QEMU and Microsoft Virtual PC
Overview
The VGA can be divided in several parts. Historically, the predecessor of the VGA - the EGA - had several chips to perform each part in the system. These chips could be configured to your liking using the I/O Bus. On the VGA these have been merged into one chip (with the exception of the DAC).
The following diagram shows which units are responsible for which parts:
This diagram is however an simplification for the ease of programming, and should not be considered correct.
VGA Registers
todo: how to read/write registers
Video Memory Layout
The video memory consists of four 'planes' (individual units) of memory, each with a size of 64KB, giving the VGA 256k of video memory. Connected to it is the Sequencer, which interprets this memory to generate colors which are fed to the subsequent stages. The way colors are organized in this memory mainly depends on the color depth.
Memory Layout in 16-color graphics modes
16 colors means there are 4 bits used per color. The VGA has four planes, and for each pixel, and each plane holds one bit of each pixel drawn. Since the information for each pixel is scattered over four memory locations, this is the most difficult memory model.
Bit 7 of each address contains information about the first pixel, Bit 6 has information about the next pixel, and so on.
Plane 0 contains the first bits of all pixels, Plane 1 the second bits and so on.
Example:
| one byte | ||||||||
|---|---|---|---|---|---|---|---|---|
| Bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Plane 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| Plane 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| Plane 2 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
| Plane 3 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| Colors displayed | 0000 (0) | 1100 (12) | 0110 (6) | 1010 (10) | 0011 (3) | 1111 (15) | 0101 (5) | 1001 (9) |
Memory Layout in 256-color graphics modes
In this mode, each byte of video memory describes exactly one pixel. Pixels are generated by increasing address in linear mode, with all colors taken from plane 0. In planar mode (Also known as Mode X) each address describes 4 consecutive pixels, one from each plane. Plane 0 describing the first pixel, plane 1 the next, and so on.
Memory Layout in text modes
In text mode, the screen is divided into character cells rather than pixels. Only three of the four planes are actually in use. Plane 0 contains the character codes for each cell, Plane 1 contains the respective attributes.
Plane 2 contains the font data. For each of the 256 available characters this plane has 32 bytes reserved. Each byte represents one horizontal cross section through each character. The first byte of each group defines the top line, each next byte describes the rows below it. For every set bit, the foreground color is used, For every cleared bit, the background color is used.
Although 32 bytes are reserved for each character, only 14 are commonly in used.
Memory Layoud in 4-bit modes
Todo: i know close to nothing about 4-bit color modes, kindof before my age
The Graphics Controller
The Graphics Controller (Abbreviated to GC) is responsible for directing memory reads and writes to and from video memory.
The memory consists of four planes of 64k on a standard VGA. Each read and write operation selects one address within all of these planes, then operates on all four planes. This means that for each byte of data written, four bytes of video memory might potentially be changed.
Apart from a few standard modes, the implementation of various control bits vary between implementations. However, the exact details can be probed by performing writes in the mode to check, then reading it out in planar mode.
These modes seem to be consistent among all VGA compatibles and emulators i've tested:
- Mode 3 (Text mode) (right now I can only set it by keeping a state dump of VGA registers of the old mode)
- Mode X (Planar 256 color mode)
I have yet to write code that enters the following standard modes on all hardware
- Mode 13h (Linear 256 color mode) - GC part seems ok, however, I cant get the sequencer to work properly (Video output is bogus)
- Mode 11h (Planar 16 color mode) - Not tried
- Mode 04h (4 color mode) - Not tried
The Graphics Controller consists of of some addressing logic, and some specific read/write logic.
The Addressing logic controls the address in video memory to be accessed, and to some extent, the individual pages within it.
The Read/Write logic controls which planes of the memory are actually read or written, and how these values relate to the value being sent by the CPU.
Addressing Logic
Registers involved:
| Register Name | Port | Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| Sequencer Memory Mode Register | 0x3C4 | 0x04 | Chain 4 | Odd/Even Disable |
Chain 4 Bit
Been testing the effect of Chain 4 on memory writes and output, and the results aren't consistent with one another. Chain 4 is located in the Sequencer which would mean setting/clearing it would have effect on video output. Furthermore i have been testing wether plane enable has effect in chain 4 writes.
| Bochs | Qemu | Virtual PC | ATI Card (X300) | NVidia (GeForce 6 6150) | |
|---|---|---|---|---|---|
| Chain 4 has effect on writes | Yes | Yes | Yes | Yes | Yes |
| Chain 4 has effect on output | Yes | No | No | No | No |
| Plane Write Enable takes effect on writes | No | Yes | No | Yes | Yes |
In bochs + VPC, as well as the hardware tested, Chain4 writes occur to this address:
plane = addr & 0x0003; // lower bits offset = addr & 0xfffb; // rest of the bits. multiples of 4 wont get written
In qemu writes go here:
plane = addr & 0x0003; // lower bits offset = addr >> 2; // only the first 16k of each page gets written.
Odd/Even Disable Bit
Seems to be a Don't Care bit in bochs+qemu
VPC generates some form of echo:
plane1 = addr & 0x0001; // lowest bit plane2 = plane1 + 2; // pick the other odd/even plane offset = addr & 0xfffe; // generate the offset write (plane1, offset); // write to the plane write (plane2, offset); // write to the other plane
This matches the NVidia card this, However my ATI card (and somewhat older, my V2x00 board) behaves slightly different (its pretty close though):
offset = addr & 0xffff; // generate the offset
There are probably some more things involved here, todo
Read/Write logic
The Read/Write Logic performs several operations on the written/read data, and a set of internal registers called the latches. Reading from video memory loads these latches with the value emitted by video memory. Write operations use the latches as an additional data source, apart from the data written to the host. The read/write logic has several different operation modes. These can be chosen by setting the Graphics Mode register. The VGA has four write modes and 2 read modes, which can be set independently. By default, the VGA operates in read mode 0 and write mode 0 in such a fashion that all written data goes straight to memory, and read data from each plane is or'ed together.
Registers involved:
| Register Name | Port | Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| Graphics Mode Register | 0x3CE | 0x05 | Read Mode | Write Mode | ||||||
| Map Mask Register | 0x3C4 | 0x02 | Memory Plane Write Enable | |||||||
| Enable Set/Reset Register | 0x3CE | 0x01 | Enable Set/Reset | |||||||
| Set/Reset Register | 0x3CE | 0x00 | Set/Reset Value | |||||||
| Data Rotate Register | 0x3CE | 0x03 | Logical Operation | Rotate Count | ||||||
| Bit Mask Register | 0x3CE | 0x08 | Bit Mask | |||||||
todo: Study effects of multibyte reads/writes on logic and latch operation
Write Mode 0
Write mode 0 is the standard write mode.
When a byte is written, it follows the following steps
- The input byte is rotated right by the amount specified in Rotate Count, with all bits shifted off being fed into bit 7
- The resulting byte is distributed over 4 separate paths, one for each plane of memory
- If a bit in the Enable Set/Reset register is clear, the corresponding byte is left unmodified. Otherwise the byte is replaced by all 0s if the corresponding bit in Set/Reset Value is clear, or all 1s if the bit is one.
- The resulting value and the latch value are passed to the ALU
- Depending of the value of Logical Operation, the following operation is performed:
| Value of Logical Operation | Result |
|---|---|
| 0 (0x00) | The byte from the set/reset operation is forwarded |
| 1 (0x08) | Both inputs are ANDed together |
| 2 (0x10) | Both inputs are ORed together |
| 3 (0x18) | Both inputs are XORed together |
- The Bit Mask Register is checked, for each set bit the corresponding bit from the ALU is forwarded. If the bit is clear the bit is taken directly from the Latch.
- The Memory Plane Write Enable field is ANDed with the input from the address logic. For each set bit in the result, the corresponding plane is loaded with the result.
Todo: write modes, read modes
The Sequencer
The Sequencer is responsible to convert video memory to color indexes.
TODO
Color Logic
This block revolves around the Attribute Controller, Palette RAM and DAC, which are together responsible for generating a color signal out of an index generated by the Sequencer.
TODO
The CRT Controller
The Cathode Ray Tube Controller, or CRTC, is the unit to create a video signal from the data produced by the DAC. By programming this unit you can control the resolution of your monitor, as well as some hardware overlay and panning effects.
WARNING: Improperly changing CRTC settings can be harmful to the monitor attached to it
The following diagram gives a quick overview of how the CRTC is generally configured (with register names)
Horizontal timigs are based on character clocks (multiples of 8 or 9 pixels), Vertical timings are per-scanline. Since these easily exceed the 255 limit of one byte, the Overflow Register is used to store the high-order bits.
TODO: Add more programming related information