User:Lionel/MSR Draft: Difference between revisions
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== |
== MSR's == |
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{| class="wikitable" |
{| class="wikitable sortable" |
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|- |
|- |
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! MSR |
! MSR |
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! Address |
! Address |
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! Vendor |
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! Bit |
! Bit / Description |
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! Comments. |
! Comments. |
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|- |
|- |
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| IA32_P5_MC_ADDR (P5_MC_ADDR) |
| IA32_P5_MC_ADDR (P5_MC_ADDR) |
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| 0x0 |
| 0x0 |
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| Intel |
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| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
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| Pentium Processor (05_01H) |
| Pentium Processor (05_01H) |
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| IA32_APIC_BASE (APIC_BASE) |
| IA32_APIC_BASE (APIC_BASE) |
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| 0x1B |
| 0x1B |
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| Intel / AMD |
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| See Intel Architecture Manual 3c. |
| See Intel Architecture Manual 3c. |
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| Intel Family 06 Model 1 and after support this. |
| Intel Family 06 Model 1 and after support this. |
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|} |
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== Intel Specific == |
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{| class="wikitable" |
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|- |
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! MSR |
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! Address |
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! Bit \ Description |
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! Comments. |
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|- |
|- |
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| IA32_FEATURE_CONTROL |
| IA32_FEATURE_CONTROL |
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| 0x3A |
| 0x3A |
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| Intel |
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| Control Features in Intel 64 Processor (R/W) |
| Control Features in Intel 64 Processor (R/W) |
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| If CPUID.01H: ECX[bit 5 or bit 6] = 1 |
| If CPUID.01H: ECX[bit 5 or bit 6] = 1 |
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| |
|- |
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| IA32_SAMPLE_AMD |
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== AMD Specific == |
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| 0xFF |
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| AMD |
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{| class="wikitable" |
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| N/A |
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| N/A |
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|- |
|- |
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! MSR |
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! Address |
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! Bit Description |
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! Purpose |
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|} |
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| IA32_SAMPLE_VIA |
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== VIA Specific == |
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| 0xFE |
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| VIA |
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{| class="wikitable" |
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| N/A |
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|- |
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| N/A |
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! MSR |
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! Address |
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! Bit Description |
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! Purpose |
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|} |
|} |
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Revision as of 02:08, 23 May 2015
A prototype of a list of MSR's, lifted straight from the manual.
MSR's
| MSR | Address | Vendor | Bit / Description | Comments. |
|---|---|---|---|---|
| IA32_P5_MC_ADDR (P5_MC_ADDR) | 0x0 | Intel | See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” | Pentium Processor (05_01H) |
| IA32_APIC_BASE (APIC_BASE) | 0x1B | Intel / AMD | See Intel Architecture Manual 3c. | Intel Family 06 Model 1 and after support this. |
| IA32_FEATURE_CONTROL | 0x3A | Intel | Control Features in Intel 64 Processor (R/W) | If CPUID.01H: ECX[bit 5 or bit 6] = 1 |
| IA32_SAMPLE_AMD | 0xFF | AMD | N/A | N/A |
| IA32_SAMPLE_VIA | 0xFE | VIA | N/A | N/A |