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User:Greasemonkey/Intel GenX: Difference between revisions
Ring buffers
(→Getting a display: Gen6-compatible code, and a few fixes) |
(Ring buffers) |
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genx_reg32[PIPEnSRC(genx_pipe)] = ((vis_stretch_w-1)<<16)|(vis_stretch_h-1);
</pre>
==Getting the ring buffer to work==
Tested on:
* GM45 1366x768 CQ60-210TU
(No Gen6 behaviour information yet! This is all about Gen4.5)
===References for RING_BUFFER_* registers===
* G45: Vol1a, pg 238
===References for commands===
* G45: Vol1b
===General notes===
The ring buffer is vital for being able to send commands to the GPE (Geometry Processing Engine) and whatnot. Commands are at least 1 DWord long, but the ring buffer indices are aligned to the nearest QWord.
Note, the tail indicates the end of the buffer, and is where you write your commands to. The head indicates the start of the buffer, and is where the GPU reads from. While the head is DWord-aligned, the tail is QWord-aligned, so you may need to pad your instructions by inserting a MI_NOOP (0x00000000 will do).
It's possible to start the ring buffer and then advance the tail when you have a new command or batch of commands.
RING_BUFFER_START denotes the address relative to that AGP stolen memory space.
RING_BUFFER_HEAD and RING_BUFFER_TAIL need to be given byte offsets, so if you add, say, two DWords, you'd add 8 to RING_BUFFER_TAIL.
Apparently you don't need a GTT to get this working.
If you want to check to see if this is working, NOPID is a useful register.
==See Also==
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