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User:Greasemonkey/Intel GenX: Difference between revisions
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Ring buffer tested on Gen6, appears to actually work
(Ring buffers) |
(Ring buffer tested on Gen6, appears to actually work) |
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The Intel GenX GPU architecture (probably) covers the Intel HD and the later Intel GMA series of GPUs, starting with the Intel 965. Later revisions tend to add and remove and readd and relocate features and instructions over time, but otherwise remain fairly similar.
This will cover Gen4 (963, 965, G35) and later. Earlier GPUs do not have open documentation and are apparently very different.
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Tested on:
* GM45 1366x768 CQ60-210TU
* HD3000 1366x768 dv6-6c35tx
===References for RING_BUFFER_* registers===
* G45: Vol1a, pg 238
* HD3000: Vol1p3, pg 39
===References for commands===
* G45: Vol1b
* HD3000: Vol1p3-5
===General notes===
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Apparently you don't need a GTT to get this working.
If you want to check to see if this is working, NOPID is a useful register. The Gen6 docs seem to be missing the location of this register, however it is in the same location as Gen4.5 (0x02094).
==See Also==
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