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User:Greasemonkey/Intel GenX: Difference between revisions
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→Getting a display: Gen6-compatible code, and a few fixes
(references are safer than replicating the manuals. also, updated VGA disabling method.) |
(→Getting a display: Gen6-compatible code, and a few fixes) |
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Tested on:
* GM45 1366x768 CQ60-210TU
* HD3000 1366x768 dv6-6c35tx
===Proper mode switch methodology===
Line 43 ⟶ 44:
===Simplified version===
This assumes that the BIOS configured the LVDS panel properly and/or in a way that we can just take its values and run with them. If it does, you can avoid an awful lot of pain
This also assumes that your panel is less than 2048 pixels wide, but that can be fixed by adding a few "if" statements. However, the 1366x768 assumption is dropped from this version.
There is a chance that this will work on systems that don't have an LVDS panel, but you will be limited to whatever resolution the BIOS spews out.
If you want a non-native resolution, enable the panelfitter and adjust PIPEBSRC to suit. Note, the panelfitter does love to blur everything.▼
▲If you want a non-native resolution, enable the panelfitter and adjust
Here's how you get from VGA text mode to native 32bpp full-res BGRX mode the easy way, and by easy we mean this is very much empirical, about as risky, and assumes the BIOS doesn't have stupid bugs in it - but may be more reliable than the version above:▼
▲Here's how you get from VGA text mode to native 32bpp full-res BGRX mode the easy way, and by easy we mean this is very much empirical, about as risky, and assumes the BIOS doesn't have stupid bugs in it
<pre>
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wait_us(100);
//
// WARNING: Gen5 changes the location of this register!
//
int real_VGACNTRL = (genx_typ < 0x5000 ? VGACNTRL : VGACNTRL_ILK);
genx_pipe = (genx_reg32[real_VGACNTRL]>>29)&1;
genx_reg32[VGACNTRL] |= (1<<31);▼
// Disable VGA
// Disable Display n
// XXX: Lacking information on DevSNB's panelfitter.
genx_reg32[DSPBCNTR] &= ~(1<<31); // Disable Display B▼
// Seems to work fine without disabling it.
▲ genx_reg32[PIPEBCONF] &= ~(1<<31); // Disable Pipe B
// For Gen4.5, however, disabling it is pretty much mandatory,
while((genx_reg32[PIPEBCONF] & (1<<30))) {} // Wait for Pipe B to stop▼
// unless you can't stand GPUs that lack antialiasing.
if(genx_typ >= 0x5000)
{
genx_reg32[PIPEnCONF(genx_pipe)] &= ~(1<<31); // Disable Pipe n
▲ // Set PIPEBSRC to screen resolution
▲ uint32_t vis_w = (genx_reg32[HTOTAL_B] & 0xFFFF)+1;
▲ uint32_t vis_h = (genx_reg32[VTOTAL_B] & 0xFFFF)+1;
▲ genx_reg32[PIPEBSRC] = ((vis_w-1)<<16)|(vis_h-1);
}
▲ genx_reg32[PFIT_CONTROL] &= ~(1<<31); // Disable panelfitter
▲ genx_reg32[PIPEBCONF] |= (1<<31); // Enable Pipe B
// Set up Display
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
</pre>
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===Setting monitor timings===
Not tested on the dv6-6c35tx.
If you need to set the monitor timings, this code should be useful for a start. These timings work on the CQ60-210TU's surprisingly tolerant LVDS panel:
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uint32_t vis_blank_w = vis_sblank_w + vis_sync_w + vis_eblank_w;
uint32_t vis_blank_h = vis_sblank_h + vis_sync_h + vis_eblank_h;
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
genx_reg32[
</pre>
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