User:Demindiro/SBI: Difference between revisions
(Initial page on SBI. Describes a caveat with sbi_set_timer) |
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The timer extension has a single function <code>sbi_set_timer</code> with FID 0x00. It takes a single <code>uint64_t</code> argument. |
The timer extension has a single function <code>sbi_set_timer</code> with FID 0x00. It takes a single <code>uint64_t</code> argument. |
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To reset the timer, pass <code>UINT64_MAX</code>. This clears the <code>STIP</code> bit and effectively disables the timer. |
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Before calling it, ensure that STIE is cleared! Otherwise you may get sporadic interrupts. i.e: |
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<source lang="asm"> |
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li s0, 1 << 5 |
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csrc sie, s0 |
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li a7, 0x54494d45 |
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li a6, 0 |
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ecall |
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csrs sie, s0 |
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</source> |
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{{NoteBox |
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| QEMU as of 6.1.0-rc3 [https://gitlab.com/qemu-project/qemu/-/issues/493 does not handle <code>UINT64_MAX</code> properly]. To fix this, apply the following patch: |
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<pre style="text-align:left"> |
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diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c |
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index 0f41e5ea1c..e65e71e5ec 100644 |
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--- a/hw/intc/sifive_clint.c |
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+++ b/hw/intc/sifive_clint.c |
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@@ -61,6 +61,8 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value, |
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/* back to ns (note args switched in muldiv64) */ |
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
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muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); |
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+ /* ensure next does not overflow, as timer_mod takes a signed value */ |
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+ next = MIN(next, INT64_MAX); |
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timer_mod(cpu->env.timer, next); |
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} |
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</pre> |
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}} |
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== See Also == |
== See Also == |
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* [https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc RISC-V Supervisor Binary Interface Specification] |
* [https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc RISC-V Supervisor Binary Interface Specification] |
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[[:Category:RISC-V]] |
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[[Category:User drafts]] |
Latest revision as of 20:38, 16 June 2024
The RISC-V SBI (Supervisor Binary Interface) defines a common interface for RISC-V platforms for OSes. It hides platform-specific implementation details such that OSes are more portable.
Notably, it adds methods to facilitate IPI (Inter-Processor Interrupts).
The reference implementation is OpenSBI.
OpenSBI on QEMU
To run OpenSBI on QEMU, download the source and compile with make PLATFORM=generic CROSS_COMPILE=riscv64-your-os-
. Then add -bios path/to/opensbi/build/platform/generic/firmware/fw_jump.bin
fw_jump vs fw_payload vs fw_dynamic
fw_jump
should be used in conjunction with QEMU's-kernel
option
fw_payload
should directly include the kernel binary.
fw_dynamic
should be used if you use another bootloader that passes more information to OpenSBI.
Interface
The calling convention is the RISC-V ELF psABI. This means you'll need to save caller-saved registers!
The main difference is that the EID (Extension ID) goes into a7
and FID (Function ID) into a6
.
Extensions
Avoid the legacy extensions (EID 0x00 - 0xFF) as those are deprecated.
Timer (0x54494D45)
The timer extension has a single function sbi_set_timer
with FID 0x00. It takes a single uint64_t
argument.
To reset the timer, pass UINT64_MAX
. This clears the STIP
bit and effectively disables the timer.
UINT64_MAX
properly. To fix this, apply the following patch:
diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c index 0f41e5ea1c..e65e71e5ec 100644 --- a/hw/intc/sifive_clint.c +++ b/hw/intc/sifive_clint.c @@ -61,6 +61,8 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value, /* back to ns (note args switched in muldiv64) */ next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); + /* ensure next does not overflow, as timer_mod takes a signed value */ + next = MIN(next, INT64_MAX); timer_mod(cpu->env.timer, next); }
See Also
External Links