TLB

Translation Lookaside Buffer

Implementation

A TLB is a cache of memory translations (i.e. page table entries). When the processor needs to translate a given virtual address into a physical address, the TLB is checked first. On x86 systems, TLB misses are handled transparently by hardware. Only if the page table entry (or any higher level directory entry) is not present will the operating system be notified.

Implications for OSDev

Like a cache, the TLB is mostly transparent. There are some cases which the OS must be aware of:

1. writing to page tables

   The TLB is not aware of changes you make to the page tables (at any level). If you make a change, you must flush the TLBs. On x86, this can be done by writing to the page table base register (CR3). That is:
   

   mov EAX, CR3
mov CR3, EAX

   Note: setting the global (G) bit in a page table entry will prevent that entry from being flushed. This is useful for pinning interrupt handlers in place.

   An alternate and better method however is to use the invlpg instruction, which should be used instead of the above method when doing small mapping modifications (creation, removing, changing).

2. multi-processor consistency

   The above is more complicated in the multi-processor case. If another processor could also be affected by a page table write (because of shared memory, or multiple threads from the same process), you must also flush the TLBs on those processors. This will require some form of inter-processor communication.

Links

• TLB at Wikipedia