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Interrupt Service Routines: Difference between revisions
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give information on how the cpu calls the handlers
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(note that in long mode you need to use iretq rather than iret) |
(give information on how the cpu calls the handlers) |
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An ISR is called directly by the CPU, and the protocol for calling an ISR differs from calling e.g. a C function. Most importantly, an ISR has to end with the <tt>iret</tt> opcode (or <tt>iretq</tt> in long mode—yes, even when using intel syntax), whereas usual C functions end with <tt>ret</tt> or <tt>retf</tt>. The obvious but nevertheless wrong solution leads to one of the most "popular" triple-fault errors among OS programmers.
== When the Handlers are Called ==
=== x86 ===
When the CPU calls the interrupt handlers, the CPU pushes these values onto the stack in this order:
<pre>
EFLAGS -> CS -> EIP
</pre>
The CS value is padded with two bytes to form a doubleword.
If the gate type is a trap gate, the CPU will clear the interrupt flag. If the interrupt is an exception, the CPU will push an error code onto the stack, as a doubleword.
The CPU will load the segment-selector value from the associated IDT descriptor into CS.
=== x86-64 ===
When the CPU calls the interrupt handlers, it changes the value in the RSP register to the value specified in the IST, and if there is none, the stack stays the same. Onto the new stack, the CPU pushes these values in this order:
<pre>
SS:RSP (original RSP) -> RFLAGS -> CS -> RIP
</pre>
CS is padded to form a quadword.
If the interrupt is called from a different ring, SS is set to 0, indicating a null selector. The CPU will modify the RFLAGS register, setting the TF, NT, and RF bits to 0. If the gate type is a trap gate, the CPU will clear the interrupt flag.
If the interrupt is an exception, the CPU will push an error code onto the stack, padded with bytes to form a quadword.
The CPU will load the segment-selector value from the associated IDT descriptor into CS, and check to ensure that CS is a valid code segment selector.
== The Problem ==
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