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Intel 8254x: Difference between revisions
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some IO info
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* A four wire serial EEPROM interface as well as a generic EEPROM "read" interface is implemented within the configuration registers.
* D0 and D3 power states are supported through ACPI.
== Programming ==
=== Detection ===
Section 5.2 in the 8254x Software Developer's Manual lists the Vendor and Device ID's of the various device in the 8254x series. These are used to detect devices on the PCI bus by looking in the PCI Configuration Space registers.
The device will also fill in the PCI Base Address Registers (BAR). BAR0 will either be a 64-bit or 32-bit MMIO address that points to the device's base register space. BAR0 should always be used to interface with the device via MMIO as the BAR number never changes in different devices in the series.
There is also a BAR that will contain an I/O base address, this can be detected by looking at each BAR and testing bit 1.
When using MMIO, reading/writing to/from registers is very straight-forward.
*(uint32_t *)(ioaddr + reg) = val; // writes "val" to an MMIO address
val = *(uint32_t *)(ioaddr + reg); // reads "val" from an MMIO address
When using IO, reading/writing to/from registers is a little more complicated as the IO address space for the 8254x is only 8 bytes wide.
The register at offset 0x00 is the "IOADDR" window. The register at offset 0x04 is the "IODATA" window.
IOADDR holds the IO address that the IODATA window operates on. So, basic operation is to set the IOADDR window and then the desired action using the IODATA window.
out32(ioaddr + 0x00, reg); // set the IOADDR window
out32(ioaddr + 0x04, val); // write the value to the IOADDR window which will end up in the register in IOADDR
in32(ioaddr + 0x04); // read back the value
== Emulation ==
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