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ISA DMA: Difference between revisions
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woops, fixed a couple links I just broke
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interrupt. This implies that all peripherals using an ISA DMA channel are limited to no more than 64 KB transfers for fear of upsetting the DMA controller.
Even with the PC/AT, IBM began bypassing the ISA DMA used in the PC/XT and used [[ATA PIO Mode]] for the hard disk. This
was because of the 64 KB limitations outlined above and the fact that the 286 processor could perform 16 bit transactions at 6 MHz. Even the ISA bus could
run at a speed of up to 12 MHz, far faster than the 4.77 MHz the DMA controller was running at.
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This creates two serious problems. One is "contention issues". The other is that it is difficult to be sure what state the flip-flop is currently in.
The standard solution for dealing with the flip-flop state issue is to reset the flip-flop to "low byte" state every single time you want to use it, just
so you can be certain it is in the proper state before sending bytes. There are only two solutions to "contention": either use a [[lock]], or allow only
one ISA DMA driver, so that contention is impossible.
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The master and slave DMA controllers are very similar, so (to save space) both of them have been combined into the following table. Please try
not to let this confuse you.
Note: for Address and Count Registers on channels 5 to 7, see [[#16 bit issues|16 bit issues]] above.
Each 8237A has 18 registers, addressed via the I/O Port bus:
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|0xC0
|Word
|
|Start Address Register channel 0/4 (unusable)
|-
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