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Detecting CPU Speed: Difference between revisions
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Major formatting changes, except for "Without Interrupts" section.
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==What is CPU Speed==
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How quickly a CPU can execute code is important for determining the CPU's performance. How fast a CPU's clock is running is only useful for specific cases (e.g. calibrating the CPU's TSC to use for measuring time).
There are also several different measurements for these different "CPU speeds":
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For example, look at a modern Intel Core i7 CPU (with turbo-boost, power management and hyper-threading). The best case instructions per second would occur when:
# There is no throttling/power saving at all.
# Only one logical CPU is running (turbo-boost activated and hyper-threading not being used)
# Simple instructions with no dependencies in a loop that fits in the CPU's "loop buffer" are being executed
# There are no branch mispredictions
# There are no accesses to memory (no data being transferred to/from caches or RAM)
The current instructions per second is the instructions per second at a specific instant in time and must be somewhere between the best and worst cases. It can't
==General Method==
In order to tell what
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Once these two sub-problems are solved, one can easily tell the CPU speed
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Note that except for very special cases, using a busy-loop (even calibrated) to introduce delays is a bad idea and that it should be kept for very small delays
(nano or micro seconds) that
Also note that PC emulators (like BOCHS, for instance) are rarely realtime,
than expected.
=== Waiting for a given amount of time ===
There are two circuits in a PC
The PIT has two operating
# the ''periodic interrupt'' mode (0x36), in which a signal is emitted to the interrupt controller at a fixed frequency. This is especially interesting on PIT channel 0 which is bound to IRQ0 on a PC.
# the ''one shot'' mode (0x34), in which the PIT will decrease a counter at its top speed (1.19318 MHz) until the counter reaches zero.
Whether or not an IRQ is fired by channel0 in 0x34 mode should be checked.
Note that theoretically,
=== Knowing how many cycles your loop takes ===
This step depends on
a well-known and deterministic amount of clock cycles to execute. This
the programmer to tell exactly how many cycles a loop iteration took by looking
up the timing of each instruction and then
Since the multi-pipelined architecture of the Pentium
no longer communicated (for a major part because the same instruction could have
variable timings depending on its surrounding, which makes the timing almost useless).
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</source>
A simple xor instruction takes one cycle,
E.g. [http://www.sylvain-ulg.be.tf/resources/speed.c looping on a chain of 1550 XORs] may require a hundred of iterations before it stabilizes around 1575 clock cycles on a AMDx86-64
Despite this inaccuracy, it gives relatively good results across the whole processor generation given a reasonably accurate timer.
A Pentium developer has a much better tool to tell timings: the
[http://www.math.uwaterloo.ca/~~jamuir/rdtscpm1.pdf rdtscpm1.pdf] explains how that feature can be used for performance monitoring and should provide the necessary information on how to access the TSC on a Pentium.
===RDTSC Instruction Access===
The presence of the Time Stamp Counter (and thus the availability of RDTSC instruction) can be detected through the [CPUID] instruction.
Note that prior to
In the case of a processor that does not support CPUID, you'll have to use more eflags-based tests to tell if
=== Working Example Code===
Some notes:
* ''irq0_count'' is a variable, which increases each time when the timer interrupt is called.
*
*
<source lang = "asm">
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</source>
See the
:- bugs report are welcome. IM to [http://www.mega-tokyo.com/forum/index.php?action=viewprofile;user=DennisCGc DennisCGC]
=== Without Interrupts ===
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I'd be tempted to say 'yes', though I haven't gave it a test nor heard of it elsewhere so far. Here is the trick:
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The [[SMBIOS]] (System Management BIOS) Specification addresses how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. The information is intended to allow generic instrumentation to deliver this information to management applications that use DMI, CIM or direct access, eliminating the need for error prone operations like probing system hardware for presence detection.
Do note that SMBIOS was never intended for
===SMBios Processor Information===
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