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→Enabling MSI: Clean up section
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=== Enabling MSI ===
First, check that the device has a pointer to the capabilities list (
Then, traverse the capabilities list. The low 8 bits of a capability register are the ID -
The MSI capability is as
{| {{wikitable}}
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| colspan="2" | Message Control
| Next
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| colspan="4" | Message Address [Low]
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| colspan="4" | [Message Address High]
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| colspan="2" | Reserved
| colspan="2" | Message Data
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| colspan="4" | [Mask]
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| colspan="4" | [Pending]
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| Reserved
| Per-vector masking
| 64
| Multiple Message Enable
| Multiple Message Capable
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The message address/data is architecture specific. On x86(-64), it is as follows:
<source lang="c">
*data = (vector & 0xFF) | (edgetrigger == 1 ? 0 : (1 << 15)) | (deassert == 1 ? 0 : (1 << 14));
return (0xFEE00000 | (processor << 12));
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'''Interrupt masking'''
If capable, you can mask individual messages by setting the corresponding bit (1 <<
If a message is pending, then the corresponding bit in the pending register is set.
Note that the PCI specification doesn't specify the location of these registers if the message address is 32
=== Enabling MSI-X ===
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