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Added "access mechanism #2"
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m (Replaced "functions" by "devices" in "For this method, there are 32 functions per bus and 256 buses, so you call "checkDevice()" 8192 times.") |
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Systems must provide a mechanism that allows access to the PCI configuration space, as most CPUs do not have any such mechanism. This task is usually performed by the Host to PCI Bridge (Host Bridge). Two distinct mechanisms are defined to allow the software to generate the required configuration accesses. Configuration mechanism #1 is the preferred method, while mechanism #2 is provided for backward compatibility. Only configuration mechanism #1 will be described here, as it is the only access mechanism that will be used in the future.
===Configuration Space Access Mechanism #1===
Two 32-bit I/O locations are used, the first location (0xCF8) is named CONFIG_ADDRESS, and the second (0xCFC) is called CONFIG_DATA. CONFIG_ADDRESS specifies the configuration address that is required to be accesses, while accesses to CONFIG_DATA will actually generate the configuration access and will transfer the data to or from the CONFIG_DATA register.
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===Configuration Space Access Mechanism #2===
This configuration space access mechanism was deprecated in PCI version 2.0. This means it's only likely to exist on hardware from around 1992 (when PCI 1.0 was introduced) to 1993 (when PCI 2.0 was introduced), which limits it to 80486 and early Pentium motherboards.
For access mechanism #2, the IO port at 0x0CF8 is an 8-bit port and is used to enable/disable the access mechanism and set the function number. It has the following format:
{| {{wikitable}}
|-
! 7 - 4
! 3 - 1
! 0
|-
| Key (0 = access mechanism disabled, non-zero = access mechanism enabled)
| Function number
| Special cycle enabled if set
|}
The IO port at 0x0CFA (the "Forwarding Register") is also an 8-bit port, and is used to set the bus number for subsequent PCI configuration space accesses.
Once the access mechanism has been enabled; accesses to IO ports 0xC000 to 0xCFFF are used to access PCI configuration space. The IO port number has the following format:
{| {{wikitable}}
|-
! 15 - 12
! 11 - 8
! 7 - 2
! 1 - 0
|-
| Must be 1100b
| Device number
| Register index
| Must be zero
|}
Note that this limits the system to 16 devices per PCI bus.
===Memory Mapped PCI Configuration Space Access===
PCI Express introduced a new way to access PCI configuration space, where it's simply memory mapped and no IO ports are used. This access mechanism is described in [[PCI Express]].
=== PCI Device Structure ===
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