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(MMU Article 1 and Article 2 merged) |
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* G, or the '''G'''lobal, flag, if set, prevents the [[TLB]] from updating the address in its cache if CR3 is reset. Note, that the page global enable bit in CR4 must be set to enable this feature.
* D, or the '''D'''irty flag, if set, indicates that page has been written to. This flag is not updated by the CPU, and once set will not unset itself.
* 0, if [https://en.wikipedia.org/wiki/Page_attribute_table PAT] is supported, shall indicate the memory type. Otherwise, it must be 0.
=== Example ===
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