Anonymous user
SSE: Difference between revisions
Jump to navigation
Jump to search
m
→X86_64: Added added regs
| [unchecked revision] | [unchecked revision] |
(→CPUID bits: Added SSSE3) |
m (→X86_64: Added added regs) |
||
Line 77:
===X86_64===
When the [[X86-64]] architecture was introduced, AMD demanded a minimum level of SSE support to simplify OS code. Any system capable of long mode should support at least SSE and SSE2, which means that the kernel does not need to care about the old FPU save code.
X86-64 adds 8 SSE registers (xmm8 - xmm15) to the mix. However, you can only access these in 64 bit mode.
==See Also==
| |||