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SSE: Difference between revisions
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Added checking for SSE
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There are 8 (16 in 64-bit mode) XMM registers (XMM0-7(15)) that come with SSE, and they are 128-bit registers. Certain SSE instructions (movntdqa, movdqa, movdqu, etc...) can load 16 bytes from memory or store 16 bytes to memory in a single operation. Also, SSE introduces a few non-temporal hint instructions (movntdqa and movntdq) that allow one-shot memory locations to be stored in non-temporal memory so those location references to do not pollute the small on-chip caches.
=== Checking for SSE ===
to check for SSE CPUID.01h:EDX.SSE[bit 25] needs to be set
<source lang="asm">
mov eax, 0x1
cpuid
test edx, 1<<25
jz .noSSE
;SSE is available
</source>
=== Adding support ===
In order to allow SSE instructions to be executed without generating a #UD, we need to alter the CR0 and CR4 registers.
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