Model Specific Registers: Difference between revisions

Processors from the P6 family onwards (including Pentium PROPentiumPro, Pentium 3II, &III, 4 and Intel Core) have a collection of registers that allowsallow configuration of variousOS-relevant things such as memory type-range, sysenter/sysexit, local APIC, etc.

Each MSR hasthat ais singleaccessed 32-bitby identificationthe numberRDMSR thatand willWRMSR begroup givenof toinstructions RDMSRis oridentified WRMSRby assemblya instructions to operate32-bit itinteger. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by [[CPUID]].01h:EDX[bit 5].

uint32_t a, d; // eax, edx

asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr));

asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));

===Other accessway to access MSRs===

As <code>rdmsr</code> and <code>wrmsr</code> are privelegedprivileged instructions. However, there are a few MSRs whichthat arecan deemedbe safeaccessed forfrom non-privelegedprivileged accesscode using special instructions. For example, the <code>rdtsc</code> instruction is a non priveleged-privileged instruction whichthat will readreads the timestamp counter, which is actually situated in an MSR (index 10h).