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Interrupts: Difference between revisions
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Linked to 8259 article
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* '''Interrupt Request (IRQ) or Hardware Interrupt''': This type of interrupt is generated externally by the chipset, and it is signalled by latching onto the #INTR pin or equivalent signal of the CPU in question. There are two types of IRQs in common use today.
** ''IRQ Lines, or Pin-based IRQs'': These are typically statically routed on the chipset. Wires or lines run from the devices on the chipset to an [[IRQ controller]] which serializes the interrupt requests sent by devices, sending them to the CPU one by one to prevent races. In many cases, an IRQ Controller will send multiple IRQs to the CPU at once, based on the priority of the device. An example of a very well known IRQ Controller is the [[8259 PIC|Intel 8259]] controller chain, which is present on all IBM-PC compatible chipsets, chaining two controllers together, each providing 8 input pins for a total of 16 usable IRQ signalling pins on the legacy IBM-PC.
** ''[[Message Based Interrupts]]'': These are signalled by writing a value to a memory location reserved for information about the interrupting device, the interrupt itself, and the vectoring information. The device is assigned a location to which it wites either by firmware or by the kernel software. Then, an IRQ is generated by the device using an arbitration protocol specific to the device's bus. An example of a bus which provides message based interrupt functionality is the PCI Bus.
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