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User:Greasemonkey/Intel GenX: Difference between revisions
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:%s/AGP/stolen memory/g
(→Memory-to-GPU blit (and vice versa): note about XY_*) |
(:%s/AGP/stolen memory/g) |
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GMAs tend to be advertised as at least two functions, so you may wish to check Function 1 as well. HDs tend to be advertised as just one.
Either way, there appears to be no difference between using BAR0 of Function 0 and BAR0 of Function 1, and only Function 0 gives
With that said, make sure you check the IDs to ensure that they match hardware that you've actually tested. Different GPUs have different bugs and thus require different workarounds - even when they're within the same family.
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Here's the information, assuming you are accessing everything through Function 0:
* uint64_t @ PCI 0x10: Location of MMIO registers. (XXX: for devices with a Function 1, this appears to do more than just MMIO registers - Function 1 should be able to provide a space with "just" MMIO registers.)
* uint64_t @ PCI 0x18: Location of
The 64-bit pointers have the lower 4 bits set to 0x4, so remember to mask it out before you use it, and remember to maintain that mask before writing back.
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</pre>
With the above config, your framebuffer should be located at the start of
===Setting monitor timings===
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It's possible to start the ring buffer and then advance the tail when you have a new command or batch of commands.
RING_BUFFER_START denotes the address relative to that
RING_BUFFER_HEAD and RING_BUFFER_TAIL need to be given byte offsets, so if you add, say, two DWords, you'd add 8 to RING_BUFFER_TAIL.
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);
genx_rb_push(((screen_height)<<16)|((screen_width)<<2)); // height in scanlines, width in bytes
genx_rb_push(
genx_rb_push(0x00330066); // XXRRGGBB - HTML colour #330066
</pre>
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genx_rb_push((0<<16) | (0)); // Y1:X1 top-left
genx_rb_push(((screen_height)<<16)|((screen_width))); // Y2:X2 bottom-right
genx_rb_push(
genx_rb_push(0x00330066); // XXRRGGBB - HTML colour #330066
</pre>
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