RISC-V: Difference between revisions
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=== Hardware Threads === |
=== Hardware Threads === |
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The RISC-V ISA specifies hardware threads, also known as ''harts'', that allow the processor to execute multiple independent streams of instructions. It is up to the processor to decide how to schedule these threads and among which of it's cores. Each hart has an ID associated with it |
The RISC-V ISA specifies hardware threads, also known as ''harts'', that allow the processor to execute multiple independent streams of instructions. It is up to the processor to decide how to schedule these threads and among which of it's cores. Each hart has an ID associated with it. |
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This is probably to abstract a control flow from the hardware, think ''Hyper Threading''. |
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=== Exceptions, Traps and Interrupts === |
=== Exceptions, Traps and Interrupts === |
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