PCI
The PCI Bus
The PCI bus was defined to establish a high performance and low cost local bus that would remain through several generations of products. By combining a transparent upgrade path from 132 MB/s (32-bit at 33 MHz) to 528 MB/s (64-bit at 66 MHz) and both 5 volt and 3.3 volt signalling environments, the PCI bus meets the needs of both low end desktop systems as well as that of high-end LAN servers. The PCI bus component and add-in card interface is processor independent, enabling an efficient transition to future processors, as well as use with multiple processor architectures. The disadvantage of the PCI bus is the limited number of electrical loads it can drive. A single PCI bus can drive a maximum of 10 loads. (Remember when counting the number of loads on the bus, a connector counts as one load and the PCI device counts as another, and sometimes two.)
Configuration Space
The PCI specification provides for totally software driven initialization and configuration of each device (or target) on the PCI Bus via a separate Configuration Address Space. All PCI devices, except host bus bridges, are required to provide 256 bytes of configuration registers for this purpose.
Configuration read/write cycles are used to access the Configuration Space of each target device. A target is selected during a configuration access when its IDSEL signal is asserted. The IDSEL acts as the classic "chip select" signal. During the address phase of the configuration cycle, the processor can address one of 64 32-bit registers within the configuration space by placing the required register number on address lines 2 through 7 (AD[7..2]) and the byte enable lines.
PCI devices are inherently little ENDIAN , meaning all multiple byte fields have the least significant values at the lower addresses. This requires a Big ENDIAN" processor, such as a Power PC, to perform the proper byte-swapping of data read from or written to the PCI device, including any accesses to the Configuration Address Space.
Systems must provide a mechanism that allows access to the PCI configuration space, as most CPUs do not have any such mechanism. This task is usually performed by the Hostto- PCI Bridge (Host Bridge). Two distinct mechanisms are defined to allow the software to generate the required configuration accesses. Configuration mechanism #1 is the preferred method, while mechanism #2 is provided for backward compatibility. Only configuration mechanism #1 will be described here, as it is the only access mechanism that will be used in the future.
Configuration Mechanism #1
Two 32-bit I/O locations are used, the first location (0xCF8) is named CONFIG_ADDRESS, and the second (0xCFC) is called CONFIG_DATA. CONFIG_ADDRESS specifies the configuration address that is required to be accesses, while accesses to CONFIG_DATA will actually generate the configuration access and will transfer the data to or from the CONFIG_DATA register.
The CONFIG_ADDRESS is a 32-bit register with the format shown in following figure. Bit 31 is an enable flag for determining when accesses to CONFIG_DATA should be translated to configuration cycles. Bits 23 through 16 allow the configuration software to choose a specific PCI bus in the system. Bits 15 through 11 select the specific device on the PCI Bus. Bits 10 through 8 choose a specific function in a device (if the device supports multiple functions). Bits 7 through 2 select the specific 32-bit area in the device's configuration space.
| 31 | 30 - 24 | 23 - 16 | 15 - 11 | 10 - 8 | 7 - 2 | 1 - 0 |
|---|---|---|---|---|---|---|
| Enable Bit | Reserved | Bus Number | Device Number | Function Number | Register Number | 00 |
The following code segment illustrates the use of configuration mechanism #1. Note that this segment, the functions sysOutLong and sysInLong are assembly language functions that make use of the OUTL and INPL Pentium assembly language instructions.
unsigned short pciConfigReadWord (unsigned short bus, unsigned short slot,
unsigned short func, unsigned short offset)
{
unsigned long address;
unsigned long lbus = (unsigned long)bus;
unsigned long lslot = (unsigned long)slot;
unsigned long lfunc = (unsigned long)func;
unsigned short tmp = 0;
/* create configuration address as per Figure 1 */
address = (unsigned long)((lbus << 16) | (lslot << 11) |
(lfunc << 8) | (offset & 0xfc) | ((UINT32)0x80000000));
/* write out the address */
sysOutLong (0xCF8, address);
/* read in the data */
tmp = (unsigned short)((sysInLong (0xCFC) >> ((offset & 2) * 8)) & 0xffff);
return (tmp);
}
When a configuration access attempts to select a device that does not exist, the host bridge will complete the access without error, dropping all data on writes and returning all ones on reads. The following code segment illustrates the read of a non-existent device.
unsigned short pciCheckVendor(unsigned short bus, unsigned short slot)
{
unsigned short vendor,device;
/* try and read the first configuration register. Since there are no */
/* vendors that == 0xFFFF, it must be a non-existent device. */
if ((vendor = pciConfigReadWord(bus,slot,0,0)) != 0xFFFF) {
device = pciConfigReadWord(bus,slot,0,2);
. . .
} return (vendor);
}
PCI Device Structure
The PCI Specification defines the organization of the 256-byte Configuration Space registers and imposes a specific template for the space. Figures 2 & 3 show the layout of the 256-byte Configuration space. All PCI compliant devices must support the Vendor ID, Device ID, Command and Status, Revision ID, Class Code and Header Type fields. Implementation of the other registers is optional, depending upon the devices functionality.
This table is applicable if the Header Type is 00h. (Figure 2)
| register | bits 31-24 | bits 23-16 | bits 15-8 | bits 7-0 |
|---|---|---|---|---|
| 00 | Device ID | Vendor ID | ||
| 04 | Status | Command | ||
| 08 | Class code | Subclass | Prog IF | Revision ID |
| 0C | BIST | Header type | Latency Timer | Cache Line Size |
| rowspan="" | | ||||
| 10 | Base address #0 (BAR0) | |||
| 14 | Base address #1 (BAR1) | |||
| 18 | Base address #2 (BAR2) | |||
| 1C | Base address #3 (BAR3) | |||
| 20 | Base address #4 (BAR4) | |||
| 24 | Base address #5 (BAR5) | |||
| 28 | Cardbus CIS Pointer | |||
| 2C | Subsystem ID | Subsystem Vendor ID | ||
| 30 | Expansion ROM base address | |||
| 34 | Reserved | Capabilities Pointer | ||
| 38 | Reserved | |||
| 3C | Max latency | Min Grant | Interrupt PIN | Interrupt Line |
This table is applicable if the Header Type is 01h (PCI-to-PCI bridge) (Figure 3)
| register | bits 31-24 | bits 23-16 | bits 15-8 | bits 7-0 |
|---|---|---|---|---|
| 00 | Device ID | Vendor ID | ||
| 04 | Status | Command | ||
| 08 | Class code | Subclass | Prog IF | Revision ID |
| 0C | BIST | Header type | Latency Timer | Cache Line Size |
| 10 | Base address #0 (BAR0) | |||
| 14 | Base address #1 (BAR1) | |||
| 18 | Secondary Latency Timer | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number |
| 1C | Secondary Status | I/O Limit | I/O Base | |
| 20 | Memory Limit | Memory Base | ||
| 24 | Prefetchable Memory Limit | Prefetchable Memory Base | ||
| 28 | Prefetchable Base Upper 32 Bits | |||
| 2C | Prefetchable Limit Upper 32 Bits | |||
| 30 | I/O Limit Upper 16 Bits | I/O Base Upper 16 Bits | ||
| 34 | Reserved | Capability Pointer | ||
| 38 | Expansion ROM base address | |||
| 3C | Bridge Control | Interrupt PIN | Interrupt Line | |
Here is the layout of the Header Type register:
| Bit 7 | Bits 6 to 0 |
|---|---|
| MF | Header Type |
MF - If MF = 1 Then this device has multiple functions.
Header Type - 00h Standard Header - 01h PCI-to-PCI Bridge - 02h CardBus Bridge
Here is the layout of the Command register:
| Bits 11 to 15 | Bit 10 | Bit 9 | Bit 8 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | Interupt Disable | Fast Back-to-Back Enable | SERR# Enable | Reserved | Parity Error Response | VGA Palette Snoop | Memory Write and Invalidate Enable | Special Cycles | Bus Master | Memory Space | I/O Space |
Interrupt Disable - If set to 1 the assertion of the devices INTx# signal is disabled; otherwise, assertion of the signal is enabled.
Fast Back-Back Enable - If set to 1 indicates a device is allowed to generate fast back-to-back transactions; otherwise, fast back-to-back transactions are only allowed to the same agent.
SERR# Enable - If set to 1 the SERR# driver is enabled; otherwise, the driver is disabled.
Bit 7 - As of revision 3.0 of the PCI local bus specification this bit is hardwired to 0. In earlier versions of the specification this bit was used by devices and may have been hardwired to 0, 1, or implemented as a read/write bit.
Parity Error Response - If set to 1 the device will take its normal action when a parity error is detected; otherwise, when an error is detected, the device will set bit 15 of the Status register (Detected Parity Error Status Bit), but will not assert the PERR# (Parity Error) pin and will continue operation as normal.
VGA Palette Snoop - If set to 1 the device does not respond to palette register writes and will snoop the data; otherwise, the device will trate palette write accesses like all other accesses.
Memory Write and Invalidate Enable - If set to 1 the device can generate the Memory Write and Invalidate command; otherwise, the Memory Write command must be used.
Special Cycles - If set to 1 the device can monitor Special Cycle operations; otherwise, the device will ignore them.
Bus Master - If set to 1 the device can behave as a bus master; otherwise, the device can not generate PCI accesses.
Memory Space - If set to 1 the device can responde to Memory Space accesses; otherwise, the device's response is disabled.
I/O Space - If set to 1 the device can respond to I/O Space accesses; otherwise, the device's response is disabled.
Here is the layout of the Status register:
| Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bits 9 and 10 | Bit 8 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bits 0 to 2 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Detected Parity Error | Signaled System Error | Recieved Master Abort | Recieved Target Abort | Signaled Target Abort | DEVSEL Timing | Master Data Parity Error | Fast Back-to-Back Capable | Reserved | 66 MHz Capable | Capabilities List | Interrupt Status | Reserved |
Detected Parity Error - This bit will be set to 1 whenever the device detects a parity error, even if parity error handling is disabled.
Signaled System Error - This bit will be set to 1 whenever the device asserts SERR#.
Recieved Master Abort - This bit will be set to 1, by a master device, whenever its transaction (except for Special Cycle transactions) is terminated with Master-Abort.
Recieved Target Abort - This bit will be set to 1, by a master device, whenever its transaction is terminated with Target-Abort.
Signaled Target Abort - This bit will be set to 1 whenever a target device terminates a transaction with Target-Abort.
DEVSEL Timing - Read only bits that represent the slowest time that a device will assert DEVSEL# for any bus command except Configuration Space read and writes. Where a value of 0x00 represents fast timing, a value of 0x01 represents medium timing, and a value of 0x02 represents slow timing.
Master Data Parity Error - This bit is only set when the following conditions are met. The bus agent asserted PERR# on a read or observed an assertion of PERR# on a write, the agent setting the bit acted as the bus master for the operation in which the error occurred, and bit 6 of the Command register (Parity Error Response bit) is set to 1.
Fast Back-to-Back Capable - If set to 1 the device can accept fast back-to-back transactions that are not from the same agent; otherwise, transactions can only be accepted from the same agent.
Bit 6 - As of revision 3.0 of the PCI local bus specification this bit is reserved. In revision 2.1 of the specification this bit was used to indicate whether or not a device supported User Definable Features.
66 Mhz Capable - If set to 1 the device is capable of running at 66 Mhz; otherwise, the device runs at 33 MHz.
Capabilities List - If set to 1 the device implements the pointer for a New Capabilities Linked list at offset 0x34; otherwise, the linked list is not available.
Interrupt Status - Represents the state of the device's INTx# signal. If set to 1 and bit 10 of the Command register (Interrupt Disable bit) is set to 0 the signal will be asserted; otherwise, the signal will be ignored.
Recall that the PCI devices follow little ENDIAN ordering. The lower addresses contain the least significant portions of the field. Software to manipulate this structure must take particular care that the endian-ordering follows the PCI devices, not the CPUs.
Base Address Registers
Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for port addresses. Typically, memory address BARs need to be located in physical ram while I/O space BARs can reside at any memory address (even beyond physical memory). To distinguish between them, you can check the value of the lowest bit. The following tables describe the two types of BARs:
| 31 - 4 | 3 | 2 - 1 | 0 |
|---|---|---|---|
| 16-Byte Aligned Base Address | Prefetchable | Type | Always 0 |
| 31 - 2 | 1 | 0 |
|---|---|---|
| 4-Byte Aligned Base Address | Reserved | Always 1 |
When you want to retrieve the actual base address of a BAR, be sure to mask the lower bits. For Memory Space BARs, you calculate (BAR & 0xFFFFFFF0). For I/O Space BARs, you calculate (BAR & 0xFFFFFFFC).
To determine the amount of address space needed by a PCI device, you must read the BAR. Devices must return 0 for address bits used internally and 1 for bits you can set. For example, if a device utilizes 16MBytes it will have BAR0 filled with 0xFF000000. You can only modify the hexadecimal FF part. This means you can only map memory on 16Mbyte boundaries. The zeroed part is used internally by the device to access memory. [1]
Disclaimer
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