Model Specific Registers: Difference between revisions
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<code>rdmsr</code> and <code>wrmsr</code> are privileged instructions. However, there are a few MSRs that can be accessed from non-privileged code using special instructions. For example, the <code>rdtsc</code> instruction is a non-privileged instruction that reads the timestamp counter, which is actually situated in an MSR (index 10h). |
<code>rdmsr</code> and <code>wrmsr</code> are privileged instructions. However, there are a few MSRs that can be accessed from non-privileged code using special instructions. For example, the <code>rdtsc</code> instruction is a non-privileged instruction that reads the timestamp counter, which is actually situated in an MSR (index 10h). |
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== |
==Additional x86_64 Registers== |
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AMD added the |
AMD added the [[CPU_Registers_x86-64#EFER|EFER]] register for controlling specific long mode features. |
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{| |
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|Bit 0 |
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|System Call Extensions (SCE) |
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|- |
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|Bits 1-7 |
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|Reserved |
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|- |
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|Bit 8 |
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|Long Mode Enable (LME) |
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|- |
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|Bit 9 |
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|Reserved |
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|- |
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|Bit 10 |
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|Long Mode Active (LMA) |
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|- |
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|Bit 11 |
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|No-Execute Enable (NXE) |
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|- |
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|Bit 12 |
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|Secure Virtual Machine Enable (SVME) |
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|- |
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|Bit 13 |
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|Long Mode Segment Limit Enable (LMSLE) |
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|- |
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|Bit 14 |
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|fast FXSAVE/FXSTOR (FFXSR) |
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|- |
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|Bit 15 |
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|Translation Cache Extension (TCE) |
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|- |
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|Bits 16-63 |
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|Reserved |
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|} |
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The by far most interesting is the SCE Bit, as it enables the <code>syscall</code> instruction. |
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==See Also== |
==See Also== |
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===Articles=== |
===Articles=== |
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*[[CPUID]] |
*[[CPUID]] |
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*[[Registers]] |
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===External Links=== |
===External Links=== |
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Revision as of 13:08, 8 July 2015
Processors from the P6 family onwards (including PentiumPro, Pentium II, III, 4 and Intel Core) have a collection of registers that allow configuration of OS-relevant things such as memory type-range, sysenter/sysexit, local APIC, etc. These MSRs are accessed using special instructions such as RDMSR (Read MSR), WRMSR (Write MSR), and RDTSC.
Accessing Model Specific Registers
Each MSR that is accessed by the RDMSR and WRMSR group of instructions is identified by a 32-bit integer. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by CPUID.01h:EDX[bit 5].
const uint32_t CPUID_FLAG_MSR = 1 << 5;
bool cpuHasMSR()
{
uint32_t a, d; // eax, edx
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
}
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi)
{
asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr));
}
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi)
{
asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
}
Other way to access MSRs
rdmsr and wrmsr are privileged instructions. However, there are a few MSRs that can be accessed from non-privileged code using special instructions. For example, the rdtsc instruction is a non-privileged instruction that reads the timestamp counter, which is actually situated in an MSR (index 10h).
Additional x86_64 Registers
AMD added the EFER register for controlling specific long mode features.