Model Specific Registers: Difference between revisions
Jump to navigation
Jump to search
[unchecked revision] | [unchecked revision] |
Content added Content deleted
m (fix cpuSetMST asm statement) |
No edit summary |
||
Line 23: | Line 23: | ||
} |
} |
||
</pre> |
</pre> |
||
==See Also== |
|||
===Articles=== |
|||
*[[CPUID]] |
|||
===External Links=== |
|||
*http://sandpile.org/ia32/msr.htm |
|||
[[Category:x86 CPU]] |
[[Category:x86 CPU]] |
Revision as of 16:52, 29 March 2007
Processors from P6 family (including Pentium PRO, Pentium 3 & 4) have a collection of registers that allows configuration of various things such as memory type-range, sysenter/sysexit, local APIC, etc.
Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by bit 5 of CPUID features.
boolean cpuHasMSR() { dword a,d; cpuid(1,&a,&d); return d&CPUID_FLAG_MSR; } void cpuGetMSR(dword msr, dword *lo, dword *hi) { asm volatile("rdsmr":"=a"(*lo),"=d"(*hi),"c"(msr)); } void cpuSetMSR(dword msr, dword lo, dword hi) { asm volatile("wrsmr"::"a"(lo),"d"(hi),"c"(msr)); }