IOAPIC
Basic Info
The Intel I/O Advanced Programmable Interrupt Controller is used to distribute external interrupts in a more advanced manner than that of the standard PIC. With the I/O APIC, interrupts can be distributed to physical or logical (clusters) of processors and can be prioritized.
Detecting I/O APIC
In order to detect the existence of an I/O APIC (or multiple ones), the Intel Multi-Processor or ACPI tables must be parsed. In the MP tables, configuration tables with the entry identification of 0x02 are for I/O APICs. Parsing will tell how many (if any) I/O APICs exist and what their ID and MMIO address is. For more information of parsing the MP tables, see the External MP Tables Links section below.
Programming the I/O APIC
IOREGSEL and IOWIN
The register IOREGSEL is an MMIO register select register that is used to access all the other I/O APIC registers. IOREGSEL only selects the register and does not actually write or read the register. The IOWIN register is the 'data' register. Once the IOREGSEL register has been set, the IOWIN register can be used to write or read the register in the IOREGSEL.
void write_ioapic_register(const ptr_t apic_base, const uint8_t offset, const uint32_t val)
{
/* tell IOREGSEL where we want to write to */
*(uint32_t*)(apic_base) = offset;
/* write the value to IOWIN */
*(uint32_t*)(apic_base + 0x10) = val;
}
uint32_t read_ioapic_register(const ptr_t apic_base, const uint8_t offset)
{
/* tell IOREGSEL where we want to read from */
*(uint32_t*)(apic_base) = offset;
/* return the data from IOWIN */
return *(uint32_t*)(apic_base + 0x10);
}
note: ptr_t is the size of the default memory reference. If a 32-bit Protected Mode setup, it's equivalent to uint32_t, and uint64_t in 64-bit Long Mode environments. note: (apic_base) is the memory base address for a selected IOAPIC, these can be found by enumerating them from the MP Tables.