NOTE: This register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
; First way:; Write:movcr0,reg; Read:movreg,cr0; ----------------------; Second way:; Write:lmswreg; Read:smswreg
CR1
Reserved, the CPU will throw a #UD exception when trying to access it.
Bits 0-11 of the physical base address are assumed to be 0. Bits 3 and 4 of CR3 are only used when accessing a PDE in 32-bit paging without PAE.
CR4
Bit
Label
Description
0
VME
Virtual 8086 Mode Extensions
1
PVI
Protected-mode Virtual Interrupts
2
TSD
Time Stamp Disable
3
DE
Debugging Extensions
4
PSE
Page Size Extension
5
PAE
Physical Address Extension
6
MCE
Machine Check Exception
7
PGE
Page Global Enabled
8
PCE
Performance-Monitoring Counter enable
9
OSFXSR
Operating system support for FXSAVE and FXRSTOR instructions
10
OSXMMEXCPT
Operating System Support for Unmasked SIMD Floating-Point Exceptions
11
UMIP
User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
13
VMXE
Virtual Machine Extensions Enable
14
SMXE
Safer Mode Extensions Enable
16
FSGSBASE
Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
17
PCIDE
PCID Enable
18
OSXSAVE
XSAVE and Processor Extended States Enable
20
SMEP
Supervisor Mode Execution Protection Enable
21
SMAP
Supervisor Mode Access Prevention Enable
22
PKE
Protection Key Enable
23
CET
Control-flow Enforcement Technology
24
PKS
Enable Protection Keys for Supervisor-Mode Pages
CR5 - CR7
Reserved, same case as CR1.
Debug Registers
DR0 - DR3
Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.
DR6
It permits the debugger to determine which debug conditions have occurred.
Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.
Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.
Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).
Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.
Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.
DR7
Bit
Description
0
Local DR0 breakpoint
1
Global DR0 breakpoint
2
Local DR1 breakpoint
3
Global DR1 breakpoint
4
Local DR2 breakpoint
5
Global DR2 breakpoint
6
Local DR3 breakpoint
7
Global DR3 breakpoint
16-17
Conditions for DR0
18-19
Size of DR0 breakpoint
20-21
Conditions for DR1
22-23
Size of DR1 breakpoint
24-25
Conditions for DR2
26-27
Size of DR2 breakpoint
28-29
Conditions for DR3
30-31
Size of DR3 breakpoint
A local breakpoint bit deactivates on hardware task switches, while a global does not.
Condition 00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).