CPU Registers x86: Difference between revisions

It permits the debugger to determine which debug conditions have occurred.<br>

Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.<br>

Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.<br>

Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).<br>

Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.<br>

Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.<br>