CPU Registers x86: Difference between revisions

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→‎General Purpose Registers: 8 bit sil, dil, bpl, spl
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Add x86-64 registers and use uppercase for acronyms
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== General Purpose Registers ==
[[Category:CPU_Registers]]

==General Purpose Registers==


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! 32 bit
! 64-bit
! 16 bit
! 32-bit
! 8 high bit
! 16-bit
! 8 low bit
! 8 high bits
! 8 low bits
! description
! Description
|-
|-
| eax
| RAX
| ax
| EAX
| ah
| AX
| al
| AH
| AL
| accumulator
| Accumulator
|-
|-
| ebx
| RBX
| bx
| EBX
| bh
| BX
| bl
| BH
| base
| BL
| Base
|-
|-
| ecx
| RCX
| cx
| ECX
| ch
| CX
| cl
| CH
| counter
| CL
| Counter
|-
|-
| edx
| RDX
| dx
| EDX
| dh
| DX
| dl
| DH
| data
| DL
| Data
|-
|-
| esi
| RSI
| si
| ESI
| SI
| N/A
| N/A
| sil
| SIL
| Source
| source index
|-
|-
| edi
| RDI
| di
| EDI
| DI
| N/A
| N/A
| dil
| DIL
| Destination
| destination index
|-
|-
| ebp
| RSP
| bp
| ESP
| SP
| N/A
| N/A
| bpl
| SPL
| Stack Pointer
| base pointer
|-
|-
| esp
| RBP
| sp
| EBP
| BP
| N/A
| N/A
| spl
| BPL
| Stack Base Pointer
| stack pointer
|-
|-
|}
|}


==Pointer Registers==
== Pointer Registers ==


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! 32 bit
! 64-bit
! 16 bit
! 32-bit
! 16-bit
! description
! Description
|-
|-
| eip
| RIP
| ip
| EIP
| IP
| instruction pointer
| Instruction Pointer
|-
|-
|}
|}


==Segment Registers==
== Segment Registers ==


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! 16 bit
! 16-bit
! Description
! description
|-
|-
| cs
| CS
| code segment
| Code Segment
|-
|-
| ds
| DS
| data segment
| Data Segment
|-
|-
| es
| ES
| Extra Segment
| extra segment
|-
|-
| ss
| SS
| Stack Segment
| stack segment
|-
|-
| fs
| FS
| General Purpose F Segment
| general purpose f segment
|-
|-
| gs
| GS
| General Purpose G Segment
| general purpose g segment
|-
|-
|}
|}


==EFLAGS Register==
== EFLAGS Register ==


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! label
! Label
! Description
! description
|-
|-
| 0
| 0
| cf
| CF
| carry flag
| Carry flag
|-
|-
| 2
| 2
| pf
| PF
| parity flag
| Parity flag
|-
|-
| 4
| 4
| af
| AF
| auxiliary flag
| Auxiliary flag
|-
|-
| 6
| 6
| zf
| ZF
| zero flag
| Zero flag
|-
|-
| 7
| 7
| sf
| SF
| sign flag
| Sign flag
|-
|-
| 8
| 8
| tf
| TF
| trap flag
| Trap flag
|-
|-
| 9
| 9
| if
| IF
| interrupt flag
| Interrupt enable flag
|-
|-
| 10
| 10
| df
| DF
| direction flag
| Direction flag
|-
|-
| 11
| 11
| of
| OF
| overflow flag
| Overflow flag
|-
|-
| 12-13
| 12-13
| iopl
| IOPL
| i/o privilege level
| I/O privilege level
|-
|-
| 14
| 14
| nt
| NT
| nested task flag
| Nested task flag
|-
|-
| 16
| 16
| rf
| RF
| resume flag
| Resume flag
|-
|-
| 17
| 17
| vm
| VM
| virtual 8086 mode flag
| Virtual 8086 mode flag
|-
|-
| 18
| 18
| ac
| AC
| alignment check flag
| Alignment check
|-
|-
| 19
| 19
| vif
| VIF
| virtual interrupt flag
| Virtual interrupt flag
|-
|-
| 20
| 20
| vip
| VIP
| virtual interrupt pending
| Virtual interrupt pending
|-
|-
| 21
| 21
| id
| ID
| Able to use CPUID instruction
| id flag
|-
|-
|}
|}


Unmarked bits are reserved.
Unlisted bits are reserved.


==Control Registers==
==Control Registers==
Line 188: Line 197:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! label
! Label
! Description
! description
|-
|-
| 0
| 0
| pe
| PE
| Protected Mode Enable
| protected mode enable
|-
|-
| 1
| 1
| mp
| MP
| monitor co-processor
| Monitor co-processor
|-
|-
| 2
| 2
| em
| EM
| x87 FPU Emulation
| emulation
|-
|-
| 3
| 3
| ts
| TS
| task switched
| Task switched
|-
|-
| 4
| 4
| et
| ET
| extension type
| Extension type
|-
|-
| 5
| 5
| ne
| NE
| numeric error
| Numeric error
|-
|-
| 16
| 16
| wp
| WP
| write protect
| Write protect
|-
|-
| 18
| 18
| am
| AM
| alignment mask
| Alignment mask
|-
|-
| 29
| 29
| nw
| NW
| not-write through
| Not-write through
|-
|-
| 30
| 30
| cd
| CD
| cache disable
| Cache disable
|-
|-
| 31
| 31
| pg
| PG
| paging
| Paging
|-
|-
|}
|}
NOTE that this register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
NOTE: This register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
<source lang="asm">
<source lang="asm">
; First way:
;way 1:
;write:
; Write:
mov cr0,reg
mov cr0, reg

;read:
; Read:
mov reg,cr0
mov reg, cr0
;----------------------
; ----------------------
;way 2:
; Second way:
;write:
; Write:
lmsw reg
lmsw reg


;read:
; Read:
smsw reg
smsw reg
</source>
</source>
Line 255: Line 265:
====CR1====
====CR1====


Reserved, the cpu will throw a #ud exeption when trying to access them.
Reserved, the CPU will throw a #UD exception when trying to access it.


====CR2====
====CR2====
Line 261: Line 271:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! label
! Label
! Description
! description
|-
|-
| 0-31 (63)
| 0-31 (63)
| pfla
| PFLA
| Page Fault Linear Address
| page fault linear address
|-
|-
|}
|}
Line 275: Line 285:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! Label
! description
! Description
! [[PAE]] mode
! [[Long Mode|long mode]]
! [[PAE]]
! [[Long Mode]]
|-
|-
| 3
| 3
| PWT
| page-level write-through (PWT)
| Page-level Write-Through
| (not used)
| (not used)
| (Not used)
| (Not used)
|-
|-
| 4
| 4
| PCD
| page-level cache disable (PCD)
| Page-level Cache Disable
| (not used)
| (not used)
| (Not used)
| (Not used)
|-
|-
| 12-31 (63)
| 12-31 (63)
| PDBR
| physical base address of page directory
| Page Directory Base Register
| base of PDPT
| base of PML4T
| Base of PDPT
| Base of PML4T
|-
|-
|}
|}
Line 302: Line 316:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! label
! Label
! Description
! description
|-
|-
| 0
| 0
| vme
| VME
| virtual 8086 mode extensions
| Virtual 8086 Mode Extensions
|-
|-
| 1
| 1
| pvi
| PVI
| protected mode virtual interrupts
| Protected-mode Virtual Interrupts
|-
|-
| 2
| 2
| tsd
| TSD
| Time Stamp Disable
| time stamp disable
|-
|-
| 3
| 3
| de
| DE
| Debugging Extensions
| debugging extensions
|-
|-
| 4
| 4
| pse
| PSE
| Page Size Extension
| page size extension
|-
|-
| 5
| 5
| pae
| PAE
| Physical Address Extension
| physical address extension
|-
|-
| 6
| 6
| mce
| MCE
| Machine Check Exception
| machine check exception
|-
|-
| 7
| 7
| pge
| PGE
| Page Global Enabled
| page global enable
|-
|-
| 8
| 8
| pce
| PCE
| Performance-Monitoring Counter enable
| performance monitoring counter enable
|-
|-
| 9
| 9
| osfxsr
| OSFXSR
| os support for fxsave and fxrstor instructions
| Operating system support for FXSAVE and FXRSTOR instructions
|-
|-
| 10
| 10
| OSXMMEXCPT
| osxmmexcpt
| Operating System Support for Unmasked SIMD Floating-Point Exceptions
| os support for unmasked simd floating point exceptions
|-
|-
| 11
| 11
| umip
| UMIP
| user mode instruction prevention (#GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
| User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
|-
|-
| 13
| 13
| vmxe
| VMXE
| Virtual Machine Extensions Enable
| virtual machine extensions enable
|-
|-
| 14
| 14
| smxe
| SMXE
| Safer Mode Extensions Enable
| safer mode extensions enable
|-
| 16
| FSGSBASE
| Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
|-
|-
| 17
| 17
| pcide
| PCIDE
| pcid enable
| PCID Enable
|-
|-
| 18
| 18
| osxsave
| OSXSAVE
| xsave and processor extended states enable
| XSAVE and Processor Extended States Enable
|-
|-
| 20
| 20
| smep
| SMEP
| Supervisor Mode Execution Protection Enable
| supervisor mode executions protection enable
|-
|-
| 21
| 21
| smap
| SMAP
| Supervisor Mode Access Prevention Enable
| supervisor mode access protection enable
|-
|-
| 22
| 22
| pke
| PKE
| Protection Key Enable
| protection keys for user-mode pages enable
|-
|-
| 23
| 23
| cet
| CET
| Control-flow Enforcement Technology
| control-flow-enforcement enable
|-
|-
| 24
| 24
| pks
| PKS
| Enable Protection Keys for Supervisor-Mode Pages
| protection keys for supervisor-mode pages enable
|-
|-
|}
|}
Line 415: Line 433:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
! Bit
! Description
! description
|-
|-
| 0
| 0
| local DR0 breakpoint
| Local DR0 breakpoint
|-
|-
| 1
| 1
| global DR0 breakpoint
| Global DR0 breakpoint
|-
|-
| 2
| 2
| local DR1 breakpoint
| Local DR1 breakpoint
|-
|-
| 3
| 3
| global DR1 breakpoint
| Global DR1 breakpoint
|-
|-
| 4
| 4
| local DR2 breakpoint
| Local DR2 breakpoint
|-
|-
| 5
| 5
| global DR2 breakpoint
| Global DR2 breakpoint
|-
|-
| 6
| 6
| local DR3 breakpoint
| Local DR3 breakpoint
|-
|-
| 7
| 7
| global DR3 breakpoint
| Global DR3 breakpoint
|-
|-
| 16-17
| 16-17
| conditions for DR0
| Conditions for DR0
|-
|-
| 18-19
| 18-19
| size of DR0 breakpoint
| Size of DR0 breakpoint
|-
|-
| 20-21
| 20-21
| conditions for DR1
| Conditions for DR1
|-
|-
| 22-23
| 22-23
| size of DR1 breakpoint
| Size of DR1 breakpoint
|-
|-
| 24-25
| 24-25
| conditions for DR2
| Conditions for DR2
|-
|-
| 26-27
| 26-27
| size of DR2 breakpoint
| Size of DR2 breakpoint
|-
|-
| 28-29
| 28-29
| conditions for DR3
| Conditions for DR3
|-
|-
| 30-31
| 30-31
| size of DR3 breakpoint
| Size of DR3 breakpoint
|-
|-
|}
|}
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).
Condition 00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).


==Test Registers==
==Test Registers==
Line 474: Line 492:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! name
! Name
! Description
! description
|-
|-
| TR3 - TR5
| TR3 - TR5
| Undocumented
| undocumented
|-
|-
| TR6
| TR6
| test command register
| Test command register
|-
|-
| TR7
| TR7
| test data register
| Test data register
|-
|-
|}
|}
Line 494: Line 512:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bits
! Nits
! label
! Label
! Description
! description
|-
|-
| 0-15
| 0-15
| limit
| Limit
| (size of [[GDT]]) - 1
| (Size of [[GDT]]) - 1
|-
|-
| 16-47
| 16-47
| base
| Base
| starting address of GDT
| Starting address of [[GDT]]
|-
|-
|}
|}
Line 513: Line 531:


{| {{wikitable}}
{| {{wikitable}}
! bits
! Bits
! label
! Label
! Description
! description
|-
|-
| 0-15
| 0-15
| limit
| Limit
| (size of [[LDT]]) - 1
| (Size of [[LDT]]) - 1
|-
|-
| 16-47
| 16-47
| base
| Base
| starting address of LDT
| Starting address of [[LDT]]
|-
|-
|}
|}
Line 532: Line 550:


{| {{wikitable}}
{| {{wikitable}}
! bits
! Bits
! label
! Label
! Description
! description
|-
|-
| 0-15
| 0-15
| limit
| Limit
| (size of [[IDT]]) - 1
| (Size of [[IDT]]) - 1
|-
|-
| 16-47
| 16-47
| base
| Base
| starting address of IDT
| Starting address of [[IDT]]
|-
|-
|}
|}


Stores the segment selector of the [[IDT]].
Stores the segment selector of the [[IDT]].

[[Category:CPU_Registers]]
Retrieved from "https://osdev.wiki/wiki/CPU_Registers_x86"