CPU Registers x86: Difference between revisions
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Added CR4 UMIP (11) bit |
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====DR6==== |
====DR6==== |
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It permits the debugger to determine which debug conditions have occurred. |
It permits the debugger to determine which debug conditions have occurred.<br> |
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Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.<br> |
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Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.<br> |
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Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).<br> |
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Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.<br> |
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Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.<br> |
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====DR7==== |
====DR7==== |