CPU Registers x86: Revision history

29 September 2021

• curprev 18:1918:19, 29 September 2021‎ osdev>Deadmutex‎ 6,508 bytes +5‎ →‎CR2: Added bit range for long mode
• curprev 18:1818:18, 29 September 2021‎ osdev>Deadmutex‎ 6,503 bytes +247‎ →‎CR3: Added PWT and PCD bits.

25 December 2020

• curprev 10:2210:22, 25 December 2020‎ osdev>1byte‎ m 6,256 bytes +173‎ →‎CR4

6 April 2019

• curprev 07:1007:10, 6 April 2019‎ osdev>Mercury0x000d‎ 6,083 bytes +29‎ →‎EFLAGS Register

11 March 2018

• curprev 23:1223:12, 11 March 2018‎ osdev>Xenos1‎ 6,054 bytes −1‎ Small misspelling fixed
• curprev 23:0623:06, 11 March 2018‎ osdev>Xenos1‎ 6,055 bytes −11‎ Fixed GPRs

3 March 2018

• curprev 19:3319:33, 3 March 2018‎ osdev>Valou3433‎ 6,066 bytes +518‎ →‎DR6

1 October 2017

• curprev 08:5808:58, 1 October 2017‎ Gijswl talk contribs‎ 5,548 bytes +117‎ Added CR4 UMIP (11) bit

16 June 2017

• curprev 14:4714:47, 16 June 2017‎ osdev>Eladashkcenazi335‎ 5,431 bytes +12‎ →‎Segment Registers
• curprev 14:1414:14, 16 June 2017‎ osdev>Eladashkcenazi335‎ 5,419 bytes +34‎ →‎Segment Registers

15 June 2017

• curprev 19:0919:09, 15 June 2017‎ osdev>Eladashkcenazi335‎ 5,385 bytes +229‎ →‎Protected Mode Registers
• curprev 19:0719:07, 15 June 2017‎ osdev>Eladashkcenazi335‎ 5,156 bytes −187‎ →‎CR0

7 June 2017

• curprev 16:3716:37, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,343 bytes +4‎ →‎CR5-7
• curprev 16:3016:30, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,339 bytes +5‎ →‎CR5-7
• curprev 16:2816:28, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,334 bytes 0‎ →‎CR5-7
• curprev 16:2816:28, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,334 bytes +16‎ →‎Control Registers
• curprev 16:2616:26, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,318 bytes −8‎ →‎CR(1, 5->7)
• curprev 16:2416:24, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,326 bytes +1‎ →‎CR(1,5->7)
• curprev 16:2416:24, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,325 bytes +92‎ →‎Control Registers
• curprev 16:2216:22, 7 June 2017‎ osdev>Eladashkcenazi335‎ 5,233 bytes +491‎ →‎CR0

9 March 2016

• curprev 17:5517:55, 9 March 2016‎ Glauxosdever talk contribs‎ 4,742 bytes +28‎ No edit summary
• curprev 17:5317:53, 9 March 2016‎ Glauxosdever talk contribs‎ 4,714 bytes −28‎ No edit summary
• curprev 17:5317:53, 9 March 2016‎ Glauxosdever talk contribs‎ 4,742 bytes +9‎ No edit summary
• curprev 17:5217:52, 9 March 2016‎ Glauxosdever talk contribs‎ 4,733 bytes −9‎ No edit summary
• curprev 17:5117:51, 9 March 2016‎ Glauxosdever talk contribs‎ 4,742 bytes +28‎ Add the page into the CPU_Registers category

10 January 2016

• curprev 11:0011:00, 10 January 2016‎ Glauxosdever talk contribs‎ 4,714 bytes +12‎ The limit fields are sizeof (GDT) - 1 and sizeof (IDT) - 1

15 December 2015

• curprev 17:5417:54, 15 December 2015‎ osdev>Cmpsb‎ m 4,702 bytes −1,132‎ Reverted edits by Cmpsb (talk) to last revision by Glauxosdev

6 December 2015

• curprev 18:2518:25, 6 December 2015‎ osdev>Cmpsb‎ 5,834 bytes +1,132‎ Added 64-bit registers, the EFER register and filled some "reserved" gaps instead of not listing the bits.

2 May 2015

• curprev 11:2411:24, 2 May 2015‎ osdev>Glauxosdev‎ m 4,702 bytes +7‎ Segment Registers ~> Protected Mode Registers (wrong caption)
• curprev 11:1611:16, 2 May 2015‎ Roman talk contribs‎ 4,695 bytes −8‎ No edit summary
• curprev 11:1311:13, 2 May 2015‎ Roman talk contribs‎ 4,703 bytes 0‎ →‎General purpose registers

1 May 2015

• curprev 08:0608:06, 1 May 2015‎ osdev>Glauxosdev‎ 4,703 bytes −144‎ Registers described in main "CPU Register" page.

30 April 2015

• curprev 14:3214:32, 30 April 2015‎ osdev>Glauxosdev‎ m 4,847 bytes +39‎ Fill LDTR based on the x86-64 article.
• curprev 14:1214:12, 30 April 2015‎ osdev>Glauxosdev‎ 4,808 bytes +182‎ Tablify DR7
• curprev 08:2508:25, 30 April 2015‎ osdev>Glauxosdev‎ 4,626 bytes +34‎ No edit summary
• curprev 08:2108:21, 30 April 2015‎ osdev>Glauxosdev‎ m 4,592 bytes 0‎ moved CPU Register x86 to CPU Registers x86: Consistency with CPU Registers x86-64

29 April 2015

• curprev 18:5118:51, 29 April 2015‎ osdev>Glauxosdev‎ m 4,592 bytes +31‎ Tablify CR3

15 March 2015

• curprev 08:1608:16, 15 March 2015‎ osdev>Glauxosdev‎ 4,561 bytes 0‎ Typo

13 March 2015

• curprev 13:5513:55, 13 March 2015‎ osdev>Bellezzasolo‎ 4,561 bytes +574‎ →‎DR7
• curprev 10:5410:54, 13 March 2015‎ osdev>Glauxosdev‎ 3,987 bytes +1‎ →‎IDTR
• curprev 10:5410:54, 13 March 2015‎ osdev>Glauxosdev‎ 3,986 bytes +126‎ →‎IDTR
• curprev 10:4610:46, 13 March 2015‎ osdev>Glauxosdev‎ m 3,860 bytes 0‎ moved CPU Register to CPU Register x86: Only x86 registers are explained
• curprev 10:4410:44, 13 March 2015‎ osdev>Glauxosdev‎ 3,860 bytes +343‎ More info about gdtr and debug registers

12 March 2015

• curprev 13:5513:55, 12 March 2015‎ osdev>Bellezzasolo‎ m 3,517 bytes +98‎ →‎Debug registers: Some info
• curprev 13:5313:53, 12 March 2015‎ osdev>Bellezzasolo‎ 3,419 bytes +177‎ →‎CR3: Filled TODO

11 March 2015

• curprev 19:1019:10, 11 March 2015‎ osdev>Glauxosdev‎ 3,242 bytes +1,273‎ merged cr0 and created missing cr4
• curprev 04:2004:20, 11 March 2015‎ osdev>Exetwezz‎ m 1,969 bytes 0‎ Registers are *in* the processor.

3 March 2015

• curprev 19:5219:52, 3 March 2015‎ osdev>Glauxosdev‎ m 1,969 bytes 0‎ moved CPU register to CPU Register: Style

2 March 2015

• curprev 15:4715:47, 2 March 2015‎ osdev>Glauxosdev‎ 1,969 bytes −55‎ →‎Pmode segmentation registers
• curprev 13:5713:57, 2 March 2015‎ osdev>Glauxosdev‎ 2,024 bytes +2,024‎ Created page with "CPU Registers are small amounts of memory located on the processor. They provide a fast way to process data. ==x86 registers== ====General purpose registers==== {| {{wikita..."