CPU Registers x86-64: Difference between revisions

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(Registers are defined in main "CPU Register" page.)
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==General purpose registers==
==General Purpose Registers==


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==Segment registers==
==Segment Registers==


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==Index registers==
==Index Registers==


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==Pointer registers==
==Pointer Registers==


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==RFLAGS register==
==RFLAGS Register==


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==Control registers==
==Control Registers==


====CR0====
====CR0====
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==Debug registers==
==Debug Registers==


====DR0 - DR3====
====DR0 - DR3====
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00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).


==Test registers==
==Test Registers==


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==Protected Mode Registers==
==Pmode segmentation registers==


====GDTR====
====GDTR====

Revision as of 11:21, 2 May 2015

General Purpose Registers

64 bit 32 bit 16 bit 8 high bit 8 low bit description
rax eax ax ah al accumulator
rbx ebx bx bh bl base
rcx ecx cx ch cl counter
rdx edx dx dh dl data

Segment Registers

16 bit description
cs code segment
ds data segment
es, fs, gs extra segment
ss stack segment

Index Registers

64 bit 32 bit 16 bit description
rsi esi si source index
rdi edi di destination index

Pointer Registers

64 bit 32 bit 16 bit description
rbp ebp bp base pointer
rsp esp sp stack pointer
rip instruction pointer

RFLAGS Register

bit label description
0 cf carry flag
2 pf parity flag
4 af auxiliary flag
6 zf zero flag
7 sf sign flag
8 tf trap flag
9 if interrupt flag
10 df direction flag
11 of overflow flag
12-13 iopl i/o priviledge level
14 nt nested task flag
16 rf resume flag
17 vm virtual 8086 mode flag
18 ac alignment check flag
19 vif virtual interrupt flag
20 vip virtual interrupt pending
21 id id flag

Control Registers

CR0

bit label description
0 pe protected mode enable
1 mp monitor co-processor
2 em emulation
3 ts task switched
4 et extension type
5 ne numeric error
16 wp write protect
18 am alignment mask
29 nw not-write through
30 cd cache disable
31 pg paging

CR1

Reserved

CR2

bit label description
0-31 pfla page fault linear address

CR3

bit description PAE mode long mode
0-31 physical base address of page directory base of PDPT base of PML4T

Note that this must be page aligned

CR4

bit label description
0 vme virtual 8086 mode extensions
1 pvi protected mode virtual interrupts
2 tsd time stamp disable
3 de debugging extensions
4 pse page size extension
5 pae physical address extension
6 mce machine check exception
7 pge page global enable
8 pce performance monitoring counter enable
9 osfxsr os support for fxsave and fxrstor instructions
10 osxmmexcpt os support for unmasked simd floating point exceptions
13 vmxe virtual machine extensions enable
14 smxe safer mode extensions enable
17 pcide pcid enable
18 osxsave xsave and processor extended states enable
20 smep supervisor mode executions protection enable
21 smap supervisor mode access protection enable

EFER

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel. Its MSR number is 0xC0000080.

Bit Label Description
0 sce system call extensions
8 lme long mode enable
10 lma long mode active
11 nxe no-execute enable
12 svme secure virtual machine enable
13 lmsle long mode segment limit enable
14 ffxsr fast fxsave/fxrstor
15 tce translation cache extension

Debug Registers

DR0 - DR3

Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.

DR6

It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.

DR7

bit description
0 local DR0 breakpoint
1 global DR0 breakpoint
2 local DR1 breakpoint
3 global DR1 breakpoint
4 local DR2 breakpoint
5 global DR2 breakpoint
6 local DR3 breakpoint
7 global DR3 breakpoint
16-17 conditions for DR0
18-19 size of DR0 breakpoint
20-21 conditions for DR1
22-23 size of DR1 breakpoint
24-25 conditions for DR2
26-27 size of DR2 breakpoint
28-29 conditions for DR3
30-31 size of DR3 breakpoint

A local breakpoint bit deactivates on hardware task switches, while a global does not.
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).

Test Registers

name description
TR3 - TR5 undocumented
TR6 test command register
TR7 test data register

Protected Mode Registers

GDTR

bits label description
0-15 limit size of GDT
16-47 base starting address of GDT

LDTR

Stores the segment selector of the LDT.

IDTR

bits label description
0-15 limit size of IDT
16-47 base starting address of IDT
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