os support for unmasked simd floating point exceptions
13
vmxe
virtual machine extensions enable
14
smxe
safer mode extensions enable
17
pcide
pcid enable
18
osxsave
xsave and processor extended states enable
20
smep
supervisor mode executions protection enable
21
smap
supervisor mode access protection enable
EFER
Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel. Its MSR number is 0xC0000080.
Bit
Label
Description
0
sce
system call extensions
8
lme
long mode enable
10
lma
long mode active
11
nxe
no-execute enable
12
svme
secure virtual machine enable
13
lmsle
long mode segment limit enable
14
ffxsr
fast fxsave/fxrstor
15
tce
translation cache extension
Debug Registers
DR0 - DR3
Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.
DR6
It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.
DR7
bit
description
0
local DR0 breakpoint
1
global DR0 breakpoint
2
local DR1 breakpoint
3
global DR1 breakpoint
4
local DR2 breakpoint
5
global DR2 breakpoint
6
local DR3 breakpoint
7
global DR3 breakpoint
16-17
conditions for DR0
18-19
size of DR0 breakpoint
20-21
conditions for DR1
22-23
size of DR1 breakpoint
24-25
conditions for DR2
26-27
size of DR2 breakpoint
28-29
conditions for DR3
30-31
size of DR3 breakpoint
A local breakpoint bit deactivates on hardware task switches, while a global does not.
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).