ADMA

Multiword DMA and UDMA modes require a driver to create a PRDT to handle the controller half of DMA transfers, and additionally send READ DMA and WRITE DMA commands to the ATA device for each PRD entry in the table, through the controller. This is really quite stupid, unless there is some problem with the controller initiating the READ/WRITE commands to the drive, itself.

ADMA is a feature of some PCI disk controllers, that eliminates the need for the driver to send the READ and WRITE commands to the drive. The Bus Mastering Controller sets up both sides of every DMA transfer, and initiates the transfer itself. All the driver needs to do is set up a table of "commands" (a CPB), set some pointers, and then turn on ADMA mode. This would allow the CPU to avoid doing any IO port commands, and would free up tremendous amounts of CPU time, if you can find a disk controller that supports it.

An ADMA capable controller maps all the standard ATA IO ports into 1K of memory at some 64-bit address (less than 256 bytes is currently used), including all the registers needed to control the ADMA function.

ADMA is supposedly built to unleash the inherent power of Queued and Overlapped ATA command sets, but neither is necessary to run ADMA, and ADMA can handle both ATA and ATAPI commands.

Since ADMA relies on 64 bit memory addresses, it seems reasonable to assume that it will only be available on disk controllers built into motherboards built for 64 bit CPUs.

Note: The CPB list contains things called PRDs, but they are not formatted the same as PRDT PRDs (like the ones that are used in ATA DMA).

Detection and Initialization

An ADMA capable disk controller must have a very specific set of codes in its PCI Configuration Space. DevID=1841h RevID= 40h ClassCode =010520h (Non-Chained Controller) 010530h (Chained Controller)

BAR4 | BAR5 (64 bits!), contains the base address for the 64 bit memory mapped ADMA registers.

See Also

External Links

• http://www.t13.org/Documents/UploadedDocuments/technical/e00149r0.pdf -- Initial specification

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