ADMA: Difference between revisions
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| ⚫ | ADMA is a feature of some PCI ATA controllers, ADMA eliminates the need for the driver to send the READ and WRITE commands to the drive. The Bus Mastering Controller sets up <b>both</b> sides of every DMA transfer, and initiates the transfer itself. All the driver needs to do is set up a table of "commands" (a CPB), set some pointers, and then turn on ADMA mode. This greatly reduces excessive IO operations, and frees up precious CPU time. |
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Multiword DMA and UDMA modes require a driver to create a PRDT to handle the controller half of DMA transfers, and additionally send READ DMA and WRITE DMA commands to the ATA device for each PRD entry in the table, through the controller. This is really quite stupid, unless there is some problem with the controller initiating the READ/WRITE commands to the drive, itself. |
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An ADMA capable controller maps the standard ATA IO and ADMA registers at a 64-bit or 32-bit address (...PCI BAR 4/5, 20h-27h). The size of this area is 1024 bytes. |
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| ⚫ | ADMA is a feature of some PCI |
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An ADMA capable controller maps all the standard ATA IO ports into 1K of memory at some 64-bit address (less than 256 bytes is currently used), including all the registers needed to control the ADMA function. |
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The ATA/ATAPI Host Adapters Standard specifies a PCI Class Code, details initialization, and operation of ADMA devices. |
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Since ADMA relies on 64 bit memory addresses, it seems reasonable to assume that it will only be available on disk controllers built into motherboards built for 64 bit CPUs. |
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Note: The CPB list contains things called PRDs, but they are not formatted the same as PRDT PRDs (like the ones that are used in ATA DMA). |
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7.4.1.6 PCI Class Code / Table 14 – ADMA PCI Class Code |
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An ADMA capable disk controller must have a very specific set of codes in its PCI Configuration Space. |
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* Programming Interface Code: 20h – Single Stepping / 30h – Continuous Operation |
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DevID=1841h |
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* Sub-class Code: 05h – ATA |
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RevID= 40h |
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* Base-Class Code: 01h – Mass Storage |
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ClassCode =010520h (Non-Chained Controller) |
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010530h (Chained Controller) |
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Several vendors have chosen ADMA mode as the basis for their SATA controller implementations, however, often these implementations contain proprietary extensions. For this reason, the PCI Class may be different... driver "quirks" may be required to support these devices. |
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BAR4 | BAR5 (64 bits!), contains the base address for the 64 bit memory mapped ADMA registers. |
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==See Also== |
==See Also== |
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===Articles=== |
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* [[ATA/ATAPI using DMA]] |
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===External Links=== |
===External Links=== |
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* http://www.t13.org/Documents/UploadedDocuments/technical/e00149r0.pdf -- Initial specification |
* http://www.t13.org/Documents/UploadedDocuments/technical/e00149r0.pdf -- Initial specification |
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* http://www.t13.org/Documents/UploadedDocuments/project/d1510r1-Host-Adapter.pdf -- Latest draft of "ATA/ATAPI Host Adapters Standard" |
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Latest revision as of 16:20, 11 February 2017
ADMA is a feature of some PCI ATA controllers, ADMA eliminates the need for the driver to send the READ and WRITE commands to the drive. The Bus Mastering Controller sets up both sides of every DMA transfer, and initiates the transfer itself. All the driver needs to do is set up a table of "commands" (a CPB), set some pointers, and then turn on ADMA mode. This greatly reduces excessive IO operations, and frees up precious CPU time.
An ADMA capable controller maps the standard ATA IO and ADMA registers at a 64-bit or 32-bit address (...PCI BAR 4/5, 20h-27h). The size of this area is 1024 bytes.
ADMA supports Queued and Overlapped ATA command sets, but neither is necessary to support ADMA. Both the ATA and ATAPI commands sets are supported.
Detection and Initialization
The ATA/ATAPI Host Adapters Standard specifies a PCI Class Code, details initialization, and operation of ADMA devices.
7.4.1.6 PCI Class Code / Table 14 – ADMA PCI Class Code
- Programming Interface Code: 20h – Single Stepping / 30h – Continuous Operation
- Sub-class Code: 05h – ATA
- Base-Class Code: 01h – Mass Storage
Several vendors have chosen ADMA mode as the basis for their SATA controller implementations, however, often these implementations contain proprietary extensions. For this reason, the PCI Class may be different... driver "quirks" may be required to support these devices.
See Also
Articles
External Links
- http://www.t13.org/Documents/UploadedDocuments/technical/e00149r0.pdf -- Initial specification
- http://www.t13.org/Documents/UploadedDocuments/project/d1510r1-Host-Adapter.pdf -- Latest draft of "ATA/ATAPI Host Adapters Standard"
