X86-64 Instruction Encoding: Difference between revisions
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→32/64-bit addressing: Added info and link |
Fixed square brackets. An expression surrounded by square brackets means: take the value at the memory address of the value of the expression |
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| Line 363: | Line 363: | ||
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! 00 |
! 00 |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + SI] |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + DI] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + SI] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + DI] |
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| style="background-color: white" |[SI] |
| style="background-color: white" |[SI] |
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| style="background-color: white" |[DI] |
| style="background-color: white" |[DI] |
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| style="background-color: white" |disp16 |
| style="background-color: white" |[disp16] |
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| style="background-color: white" |[BX] |
| style="background-color: white" |[BX] |
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|- |
|- |
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! 01 |
! 01 |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + SI + disp8] |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + DI + disp8] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + SI + disp8] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + DI + disp8] |
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| style="background-color: white" |[SI |
| style="background-color: white" |[SI + disp8] |
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| style="background-color: white" |[DI |
| style="background-color: white" |[DI + disp8] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + disp8] |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + disp8] |
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|- |
|- |
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! 10 |
! 10 |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + SI + disp16] |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + DI + disp16] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + SI + disp16] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + DI + disp16] |
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| style="background-color: white" |[SI |
| style="background-color: white" |[SI + disp16] |
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| style="background-color: white" |[DI |
| style="background-color: white" |[DI + disp16] |
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| style="background-color: white" |[BP |
| style="background-color: white" |[BP + disp16] |
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| style="background-color: white" |[BX |
| style="background-color: white" |[BX + disp16] |
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|- |
|- |
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! 11 |
! 11 |
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| Line 423: | Line 423: | ||
! 00 |
! 00 |
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| style="background-color: white" colspan="4"|[r/m] |
| style="background-color: white" colspan="4"|[r/m] |
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| style="background-color: white" |[[#SIB|SIB]] |
| style="background-color: white" |[[[#SIB|SIB]]] |
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| style="background-color: white" | |
| style="background-color: white" |[[[#RIP.2FEIP-relative_addressing|RIP/EIP]]<span style="vertical-align: super">[[#Table8Note1|1]],[[#Table8Note2|2]]</span> + disp32] |
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| style="background-color: white" colspan="6"|[r/m] |
| style="background-color: white" colspan="6"|[r/m] |
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| style="background-color: white" |[[#SIB|SIB]] |
| style="background-color: white" |[[[#SIB|SIB]]] |
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| style="background-color: white" | |
| style="background-color: white" |[[[#RIP.2FEIP-relative_addressing|RIP/EIP]]<span style="vertical-align: super">[[#Table8Note1|1]],[[#Table8Note2|2]]</span> + disp32] |
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| style="background-color: white" colspan="2"|[r/m] |
| style="background-color: white" colspan="2"|[r/m] |
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|- |
|- |
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! 01 |
! 01 |
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| style="background-color: white" colspan="4"|[r/m |
| style="background-color: white" colspan="4"|[r/m + disp8] |
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| style="background-color: white" |[[#SIB|SIB]]+disp8 |
| style="background-color: white" |[[[#SIB|SIB]] + disp8] |
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| style="background-color: white" colspan="7"|[r/m |
| style="background-color: white" colspan="7"|[r/m + disp8] |
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| style="background-color: white" |[[#SIB|SIB]]+disp8 |
| style="background-color: white" |[[[#SIB|SIB]] + disp8] |
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| style="background-color: white" colspan="3"|[r/m |
| style="background-color: white" colspan="3"|[r/m + disp8] |
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|- |
|- |
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! 10 |
! 10 |
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| style="background-color: white" colspan="4"|[r/m |
| style="background-color: white" colspan="4"|[r/m + disp32] |
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| style="background-color: white" |[[#SIB|SIB]]+disp32 |
| style="background-color: white" |[[[#SIB|SIB]] + disp32] |
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| style="background-color: white" colspan="7"|[r/m |
| style="background-color: white" colspan="7"|[r/m + disp32] |
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| style="background-color: white" |[[#SIB|SIB]]+disp32 |
| style="background-color: white" |[[[#SIB|SIB]] + disp32] |
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| style="background-color: white" colspan="3"|[r/m |
| style="background-color: white" colspan="3"|[r/m + disp32] |
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|- |
|- |
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! 11 |
! 11 |
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| Line 512: | Line 512: | ||
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! rowspan="16" | 00 !! style="text-align: left;" | 0.000 AX |
! rowspan="16" | 00 !! style="text-align: left;" | 0.000 AX |
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| style="background-color: white" rowspan="4" colspan="5"|[base |
| style="background-color: white" rowspan="4" colspan="5"|[base + (index * s)] |
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| style="background-color: white" rowspan="4"| |
| style="background-color: white" rowspan="4"|[(index * s) + disp32] |
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| style="background-color: white" rowspan="4" colspan="7" |[base |
| style="background-color: white" rowspan="4" colspan="7" |[base + (index * s)] |
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| style="background-color: white" rowspan="4"| |
| style="background-color: white" rowspan="4"|[(index * s) + disp32] |
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| style="background-color: white" rowspan="4" colspan="2"|[base |
| style="background-color: white" rowspan="4" colspan="2"|[base + (index * s)] |
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|- |
|- |
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! style="text-align: left;" | 0.001 CX |
! style="text-align: left;" | 0.001 CX |
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| Line 526: | Line 526: | ||
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
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| style="background-color: white" colspan="5"|[base] |
| style="background-color: white" colspan="5"|[base] |
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| style="background-color: white"| disp32 |
| style="background-color: white"| [disp32] |
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| style="background-color: white" colspan="7"|[base] |
| style="background-color: white" colspan="7"|[base] |
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| style="background-color: white"| disp32 |
| style="background-color: white"| [disp32] |
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| style="background-color: white" colspan="2"|[base] |
| style="background-color: white" colspan="2"|[base] |
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|- |
|- |
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! style="text-align: left;" | 0.101 BP |
! style="text-align: left;" | 0.101 BP |
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| style="background-color: white" rowspan="11" colspan="5"|[base |
| style="background-color: white" rowspan="11" colspan="5"|[base + (index * s)] |
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| style="background-color: white" rowspan="11"| |
| style="background-color: white" rowspan="11"|[(index * s) + disp32] |
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| style="background-color: white" rowspan="11" colspan="7"|[base |
| style="background-color: white" rowspan="11" colspan="7"|[base + (index * s)] |
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| style="background-color: white" rowspan="11"| |
| style="background-color: white" rowspan="11"|[(index * s) + disp32] |
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| style="background-color: white" rowspan="11" colspan="2"|[base |
| style="background-color: white" rowspan="11" colspan="2"|[base + (index * s)] |
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|- |
|- |
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! style="text-align: left;" | 0.110 SI |
! style="text-align: left;" | 0.110 SI |
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| Line 582: | Line 582: | ||
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! rowspan="16" | 01 !! style="text-align: left;" | 0.000 AX |
! rowspan="16" | 01 !! style="text-align: left;" | 0.000 AX |
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| style="background-color: white" rowspan="4" colspan="16"|[base |
| style="background-color: white" rowspan="4" colspan="16"|[base + (index * s) + disp8] |
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|- |
|- |
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! style="text-align: left;" | 0.001 CX |
! style="text-align: left;" | 0.001 CX |
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| Line 591: | Line 591: | ||
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|- |
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! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
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| style="background-color: white" colspan="16"|[base |
| style="background-color: white" colspan="16"|[base + disp8] |
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|- |
|- |
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! style="text-align: left;" | 0.101 BP |
! style="text-align: left;" | 0.101 BP |
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| style="background-color: white" rowspan="11" colspan="16"|[base |
| style="background-color: white" rowspan="11" colspan="16"|[base + (index * s) + disp8] |
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|- |
|- |
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! style="text-align: left;" | 0.110 SI |
! style="text-align: left;" | 0.110 SI |
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| Line 640: | Line 640: | ||
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|- |
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! rowspan="16" | 10 !! style="text-align: left;" | 0.000 AX |
! rowspan="16" | 10 !! style="text-align: left;" | 0.000 AX |
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| style="background-color: white" rowspan="4" colspan="16"|[base |
| style="background-color: white" rowspan="4" colspan="16"|[base + (index * s) + disp32] |
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|- |
|- |
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! style="text-align: left;" | 0.001 CX |
! style="text-align: left;" | 0.001 CX |
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| Line 649: | Line 649: | ||
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|- |
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! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP |
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| style="background-color: white" colspan="16"|[base |
| style="background-color: white" colspan="16"|[base + disp32] |
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|- |
|- |
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! style="text-align: left;" | 0.101 BP |
! style="text-align: left;" | 0.101 BP |
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| style="background-color: white" rowspan="11" colspan="16"|[base |
| style="background-color: white" rowspan="11" colspan="16"|[base + (index * s) + disp32] |
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|- |
|- |
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! style="text-align: left;" | 0.110 SI |
! style="text-align: left;" | 0.110 SI |
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