X86-64 Instruction Encoding: Difference between revisions

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! X.Reg!! 8-bit GP!! 16-bit GP!! 32-bit GP!! 64-bit GP!! 64-bit MMX!! 128-bit XMM!! 256-bit YMM!! 16-bit Segment!! 32-bit Control!! 32-bit Debug
! X.Reg!! 8-bit GP!! 16-bit GP!! 32-bit GP!! 64-bit GP!! 64-bit MMX!! 128-bit XMM!! 256-bit YMM!! 16-bit Segment!! 32-bit Control!! 32-bit Debug
|-
|-
| 0.000<sub>2</sub> (0)||AL||AX||EAX||RAX||MM0||XMM0||YMM0||ES||CR0||DR0
| b0.000 (0)||AL||AX||EAX||RAX||MM0||XMM0||YMM0||ES||CR0||DR0
|-
|-
| 0.001<sub>2</sub> (1)||CL||CX||ECX||RCX||MM1||XMM1||YMM1||CS||CR1||DR1
| b0.001 (1)||CL||CX||ECX||RCX||MM1||XMM1||YMM1||CS||CR1||DR1
|-
|-
| 0.010<sub>2</sub> (2)||DL||DX||EDX||RDX||MM2||XMM2||YMM2||SS||CR2||DR2
| b0.010 (2)||DL||DX||EDX||RDX||MM2||XMM2||YMM2||SS||CR2||DR2
|-
|-
| 0.011<sub>2</sub> (3)||BL||BX||EBX||RBX||MM3||XMM3||YMM3||DS||CR3||DR3
| b0.011 (3)||BL||BX||EBX||RBX||MM3||XMM3||YMM3||DS||CR3||DR3
|-
|-
| 0.100<sub>2</sub> (4)||AH, SPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SP||ESP||RSP||MM4||XMM4||YMM4||FS||CR4||DR4
| b0.100 (4)||AH, SPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SP||ESP||RSP||MM4||XMM4||YMM4||FS||CR4||DR4
|-
|-
| 0.101<sub>2</sub> (5)||CH, BPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||BP||EBP||RBP||MM5||XMM5||YMM5||GS||CR5||DR5
| b0.101 (5)||CH, BPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||BP||EBP||RBP||MM5||XMM5||YMM5||GS||CR5||DR5
|-
|-
| 0.110<sub>2</sub> (6)||DH, SIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SI||ESI||RSI||MM6||XMM6||YMM6||invalid||CR6||DR6
| b0.110 (6)||DH, SIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SI||ESI||RSI||MM6||XMM6||YMM6||invalid||CR6||DR6
|-
|-
| 0.111<sub>2</sub> (7)||BH, DIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||DI||EDI||RDI||MM7||XMM7||YMM7||invalid||CR7||DR7
| b0.111 (7)||BH, DIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||DI||EDI||RDI||MM7||XMM7||YMM7||invalid||CR7||DR7
|-
|-
| 1.000<sub>2</sub> (8)||R8L||R8W||R8D||R8||MM0||XMM8||YMM8||ES||CR8||DR8
| b1.000 (8)||R8L||R8W||R8D||R8||MM0||XMM8||YMM8||ES||CR8||DR8
|-
|-
| 1.001<sub>2</sub> (9)||R9L||R9W||R9D||R9||MM1||XMM9||YMM9||CS||CR9||DR9
| b1.001 (9)||R9L||R9W||R9D||R9||MM1||XMM9||YMM9||CS||CR9||DR9
|-
|-
| 1.010<sub>2</sub> (10)||R10L||R10W||R10D||R10||MM2||XMM10||YMM10||SS||CR10||DR10
| b1.010 (10)||R10L||R10W||R10D||R10||MM2||XMM10||YMM10||SS||CR10||DR10
|-
|-
| 1.011<sub>2</sub> (11)||R11L||R11W||R11D||R11||MM3||XMM11||YMM11||DS||CR11||DR11
| b1.011 (11)||R11L||R11W||R11D||R11||MM3||XMM11||YMM11||DS||CR11||DR11
|-
|-
| 1.100<sub>2</sub> (12)||R12L||R12W||R12D||R12||MM4||XMM12||YMM12||FS||CR12||DR12
| b1.100 (12)||R12L||R12W||R12D||R12||MM4||XMM12||YMM12||FS||CR12||DR12
|-
|-
| 1.101<sub>2</sub> (13)||R13L||R13W||R13D||R13||MM5||XMM13||YMM13||GS||CR13||DR13
| b1.101 (13)||R13L||R13W||R13D||R13||MM5||XMM13||YMM13||GS||CR13||DR13
|-
|-
| 1.110<sub>2</sub> (14)||R14L||R14W||R14D||R14||MM6||XMM14||YMM14||invalid||CR14||DR14
| b1.110 (14)||R14L||R14W||R14D||R14||MM6||XMM14||YMM14||invalid||CR14||DR14
|-
|-
| 1.111<sub>2</sub> (15)||R15L||R15W||R15D||R15||MM7||XMM15||YMM15||invalid||CR15||DR15
| b1.111 (15)||R15L||R15W||R15D||R15||MM7||XMM15||YMM15||invalid||CR15||DR15
|}
|}
<small id="Table2Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small>
<small id="Table2Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small>

==== 16-bit addressing ====
These are the meanings of the ''Mod'' (vertically) and ''REX/VEX/XOP.B'' and ''R/M'' bits (horizontally) for [[#Operand-size and address-size override prefix|16-bit addressing]]. ''B.R/M'' and ''Mod'' are in binary. The SIB-byte is not used in 16-bit addressing. In ''Long processing mode'' there is no way to specify 16-bit addresses.
<div style="font-size: 70%; text-align: center">
{| {{wikitable}}
! 16-bit!! colspan="16" style="text-align: left;" | B.R/M
|-
! Mod
! x.000<br />AX, R8W
! x.001<br />CX, R9W
! x.010<br />DX, R10W
! x.011<br />BX, R11W
! x.100<br />SP, R12W
! x.101<br />BP, R13W
! x.110<br />SI, R14W
! x.111<br />DI, R15W
|-
! 00
| style="background-color: white" |[BX]+[SI]
| style="background-color: white" |[BX]+[DI]
| style="background-color: white" |[BP]+[SI]
| style="background-color: white" |[BP]+[DI]
| style="background-color: white" |[SI]
| style="background-color: white" |[DI]
| style="background-color: white" |disp16
| style="background-color: white" |[BX]
|-
! 01
| style="background-color: white" |[BX]+[SI]+disp8
| style="background-color: white" |[BX]+[DI]+disp8
| style="background-color: white" |[BP]+[SI]+disp8
| style="background-color: white" |[BP]+[DI]+disp8
| style="background-color: white" |[SI]+disp8
| style="background-color: white" |[DI]+disp8
| style="background-color: white" |[BP]+disp8
| style="background-color: white" |[BX]+disp8
|-
! 10
| style="background-color: white" |[BX]+[SI]+disp16
| style="background-color: white" |[BX]+[DI]+disp16
| style="background-color: white" |[BP]+[SI]+disp16
| style="background-color: white" |[BP]+[DI]+disp16
| style="background-color: white" |[SI]+disp16
| style="background-color: white" |[DI]+disp16
| style="background-color: white" |[BP]+disp16
| style="background-color: white" |[BX]+disp16
|-
! 11
| style="background-color: white" colspan="8"|r/m
|}
</div>

==== 32/64-bit addressing ====
These are the meanings of the ''Mod'' (vertically) and ''REX/VEX/XOP.B'' and ''R/M'' bits (horizontally) for [[#Operand-size and address-size override prefix|32 and 64-bit addressing]]. ''B.R/M'' and ''Mod'' are in binary.
<div style="font-size: 70%; text-align: center">
{| {{wikitable}}
! 32/64-bit!! colspan="16" style="text-align: left;" | B.R/M
|-
! Mod
! 0.000<br />AX
! 0.001<br />CX
! 0.010<br />DX
! 0.011<br />BX
! 0.100<br />SP
! 0.101<br />BP
! 0.110<br />SI
! 0.111<br />DI
! 1.000<br />R8
! 1.001<br />R9
! 1.010<br />R10
! 1.011<br />R11
! 1.100<br />R12
! 1.101<br />R13
! 1.110<br />R14
! 1.111<br />R15
|-
! 00
| style="background-color: white" colspan="4"|[r/m]
| style="background-color: white" |[[#32-bit SIB byte|SIB]]
| style="background-color: white" |[&nbsp;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table5Note1|1]],[[#Table5Note2|2]]</span>+disp32
| style="background-color: white" colspan="6"|[r/m]
| style="background-color: white" |[[#32-bit SIB byte|SIB]]
| style="background-color: white" |[&nbsp;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table5Note1|1]],[[#Table5Note2|2]]</span>+disp32
| style="background-color: white" colspan="2"|[r/m]
|-
! 01
| style="background-color: white" colspan="4"|[r/m]+disp8
| style="background-color: white" |[[#32-bit SIB byte|SIB]]+disp8
| style="background-color: white" colspan="7"|[r/m]+disp8
| style="background-color: white" |[[#32-bit SIB byte|SIB]]+disp8
| style="background-color: white" colspan="3"|[r/m]+disp8
|-
! 10
| style="background-color: white" colspan="4"|[r/m]+disp32
| style="background-color: white" |[[#32-bit SIB byte|SIB]]+disp32
| style="background-color: white" colspan="7"|[r/m]+disp32
| style="background-color: white" |[[#32-bit SIB byte|SIB]]+disp32
| style="background-color: white" colspan="3"|[r/m]+disp32
|-
! 11
| style="background-color: white" colspan="16"|r/m
|}
</div>
<small id="Table5Note1">1: In protected/compatibility mode, this is just ''disp32'', but in long mode this is ''[RIP]+disp32'' (for 64-bit addresses) or ''[EIP]+disp32'' (for 32-bit addresses).</small><br />
<small id="Table5Note2">2: In long mode, to encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>



=== SIB ===
=== SIB ===
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! factor ''s''
! factor ''s''
|-
|-
| 00<sub>2</sub> (0)||1
| b00||1
|-
|-
| 01<sub>2</sub> (1)||2
| b01||2
|-
|-
| 10<sub>2</sub> (2)||4
| b10||4
|-
|-
| 11<sub>2</sub> (3)||8
| b11||8
|}
|}
|-
|-
Line 377: Line 483:
| SIB.base||3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
| SIB.base||3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|}
|}

==== 32/64-bit addressing ====
The meaning of the SIB byte while using 32 or 64-bit addressing is as follows. The ModR/M byte's ''Mod'' field and the SIB byte's ''index'' field are used vertically, the SIB byte's ''base'' field and REX/VEX/XOP.B bit horizontally. The ''s'' is the [[#SIBScale|scaling factor]]. ''B.Base'', ''X.Index'' and ''Mod'' are in binary.
<div style="font-size: 70%; text-align: center">
{| {{wikitable}}
! colspan="2" | !! colspan="16" style="text-align: left;" | B.Base
|-
! Mod
! style="text-align: left;" | X.Index
! 0.000<br />AX
! 0.001<br />CX
! 0.010<br />DX
! 0.011<br />BX
! 0.100<br />SP
! 0.101<span style="vertical-align: super">[[#Table5Note1|1]]</span><br />BP
! 0.110<br />SI
! 0.111<br />DI
! 1.000<br />R8
! 1.001<br />R9
! 1.010<br />R10
! 1.011<br />R11
! 1.100<br />R12
! 1.101<span style="vertical-align: super">[[#Table5Note1|1]]</span><br />R13
! 1.110<br />R14
! 1.111<br />R15
|-
! rowspan="16" | 00 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="5"|[base] + ([index] * s)
| style="background-color: white" rowspan="4"|([index] * s)<br />+ disp32
| style="background-color: white" rowspan="4" colspan="7" |[base] + ([index] * s)
| style="background-color: white" rowspan="4"|([index] * s)<br />+ disp32
| style="background-color: white" rowspan="4" colspan="2"|[base] + ([index] * s)
|-
! style="text-align: left;" | 0.001 CX
|-
! style="text-align: left;" | 0.010 DX
|-
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2|2]]</span> SP
| style="background-color: white" colspan="5"|[base]
| style="background-color: white"| disp32
| style="background-color: white" colspan="7"|[base]
| style="background-color: white"| disp32
| style="background-color: white" colspan="2"|[base]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="5"|[base] + ([index] * s)
| style="background-color: white" rowspan="11"|([index] * s)<br />+ disp32
| style="background-color: white" rowspan="11" colspan="7"|[base] + ([index] * s)
| style="background-color: white" rowspan="11"|([index] * s)<br />+ disp32
| style="background-color: white" rowspan="11" colspan="2"|[base] + ([index] * s)
|-
! style="text-align: left;" | 0.110 SI
|-
! style="text-align: left;" | 0.111 DI
|-
! style="text-align: left;" | 1.000 R8
|-
! style="text-align: left;" | 1.001 R9
|-
! style="text-align: left;" | 1.010 R10
|-
! style="text-align: left;" | 1.011 R11
|-
! style="text-align: left;" | 1.100 R12
|-
! style="text-align: left;" | 1.101 R13
|-
! style="text-align: left;" | 1.110 R14
|-
! style="text-align: left;" | 1.111 R15
|-
| colspan="18" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! colspan="2" | !! colspan="16" style="text-align: left;" | B.Base
|-
! Mod
! style="text-align: left;" | X.Index
! 0.000<br />AX
! 0.001<br />CX
! 0.010<br />DX
! 0.011<br />BX
! 0.100<br />SP
! 0.101<br />BP
! 0.110<br />SI
! 0.111<br />DI
! 1.000<br />R8
! 1.001<br />R9
! 1.010<br />R10
! 1.011<br />R11
! 1.100<br />R12
! 1.101<br />R13
! 1.110<br />R14
! 1.111<br />R15
|-
! rowspan="16" | 01 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp8
|-
! style="text-align: left;" | 0.001 CX
|-
! style="text-align: left;" | 0.010 DX
|-
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp8
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp8
|-
! style="text-align: left;" | 0.110 SI
|-
! style="text-align: left;" | 0.111 DI
|-
! style="text-align: left;" | 1.000 R8
|-
! style="text-align: left;" | 1.001 R9
|-
! style="text-align: left;" | 1.010 R10
|-
! style="text-align: left;" | 1.011 R11
|-
! style="text-align: left;" | 1.100 R12
|-
! style="text-align: left;" | 1.101 R13
|-
! style="text-align: left;" | 1.110 R14
|-
! style="text-align: left;" | 1.111 R15
|-
| colspan="18" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! colspan="2" | !! colspan="16" style="text-align: left;" | B.Base
|-
! Mod
! style="text-align: left;" | X.Index
! 0.000<br />AX
! 0.001<br />CX
! 0.010<br />DX
! 0.011<br />BX
! 0.100<br />SP
! 0.101<br />BP
! 0.110<br />SI
! 0.111<br />DI
! 1.000<br />R8
! 1.001<br />R9
! 1.010<br />R10
! 1.011<br />R11
! 1.100<br />R12
! 1.101<br />R13
! 1.110<br />R14
! 1.111<br />R15
|-
! rowspan="16" | 10 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp32
|-
! style="text-align: left;" | 0.001 CX
|-
! style="text-align: left;" | 0.010 DX
|-
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp32
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp32
|-
! style="text-align: left;" | 0.110 SI
|-
! style="text-align: left;" | 0.111 DI
|-
! style="text-align: left;" | 1.000 R8
|-
! style="text-align: left;" | 1.001 R9
|-
! style="text-align: left;" | 1.010 R10
|-
! style="text-align: left;" | 1.011 R11
|-
! style="text-align: left;" | 1.100 R12
|-
! style="text-align: left;" | 1.101 R13
|-
! style="text-align: left;" | 1.110 R14
|-
! style="text-align: left;" | 1.111 R15
|}
</div>
<small id="TableXNote1">1: No base register is encoded.</small><br />
<small id="TableXNote2">2: No index register is encoded.</small>


== Addressing modes ==
== Addressing modes ==
Retrieved from "https://osdev.wiki/wiki/X86-64_Instruction_Encoding"